avr_device/devices/atmega2560/wdt/
wdtcsr.rs

1#[doc = "Register `WDTCSR` reader"]
2pub struct R(crate::R<WDTCSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<WDTCSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<WDTCSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<WDTCSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `WDTCSR` writer"]
17pub struct W(crate::W<WDTCSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<WDTCSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<WDTCSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<WDTCSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `WDPL` reader - Watchdog Timer Prescaler - Low Bits"]
38pub type WDPL_R = crate::FieldReader<u8, WDPL_A>;
39#[doc = "Watchdog Timer Prescaler - Low Bits\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum WDPL_A {
43    #[doc = "0: - 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set"]
44    CYCLES_2K_512K = 0,
45    #[doc = "1: - 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set"]
46    CYCLES_4K_1024K = 1,
47    #[doc = "2: - 8192 cycles, ~64ms"]
48    CYCLES_8K = 2,
49    #[doc = "3: - 16K (16384) cycles, ~0.125s"]
50    CYCLES_16K = 3,
51    #[doc = "4: - 32K (32768) cycles, ~0.25s"]
52    CYCLES_32K = 4,
53    #[doc = "5: - 64K (65536) cycles, ~0.5s"]
54    CYCLES_64K = 5,
55    #[doc = "6: - 128K (131072) cycles, ~1s"]
56    CYCLES_128K = 6,
57    #[doc = "7: - 256K (262144) cycles, ~2s"]
58    CYCLES_256K = 7,
59}
60impl From<WDPL_A> for u8 {
61    #[inline(always)]
62    fn from(variant: WDPL_A) -> Self {
63        variant as _
64    }
65}
66impl WDPL_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> WDPL_A {
70        match self.bits {
71            0 => WDPL_A::CYCLES_2K_512K,
72            1 => WDPL_A::CYCLES_4K_1024K,
73            2 => WDPL_A::CYCLES_8K,
74            3 => WDPL_A::CYCLES_16K,
75            4 => WDPL_A::CYCLES_32K,
76            5 => WDPL_A::CYCLES_64K,
77            6 => WDPL_A::CYCLES_128K,
78            7 => WDPL_A::CYCLES_256K,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `CYCLES_2K_512K`"]
83    #[inline(always)]
84    pub fn is_cycles_2k_512k(&self) -> bool {
85        *self == WDPL_A::CYCLES_2K_512K
86    }
87    #[doc = "Checks if the value of the field is `CYCLES_4K_1024K`"]
88    #[inline(always)]
89    pub fn is_cycles_4k_1024k(&self) -> bool {
90        *self == WDPL_A::CYCLES_4K_1024K
91    }
92    #[doc = "Checks if the value of the field is `CYCLES_8K`"]
93    #[inline(always)]
94    pub fn is_cycles_8k(&self) -> bool {
95        *self == WDPL_A::CYCLES_8K
96    }
97    #[doc = "Checks if the value of the field is `CYCLES_16K`"]
98    #[inline(always)]
99    pub fn is_cycles_16k(&self) -> bool {
100        *self == WDPL_A::CYCLES_16K
101    }
102    #[doc = "Checks if the value of the field is `CYCLES_32K`"]
103    #[inline(always)]
104    pub fn is_cycles_32k(&self) -> bool {
105        *self == WDPL_A::CYCLES_32K
106    }
107    #[doc = "Checks if the value of the field is `CYCLES_64K`"]
108    #[inline(always)]
109    pub fn is_cycles_64k(&self) -> bool {
110        *self == WDPL_A::CYCLES_64K
111    }
112    #[doc = "Checks if the value of the field is `CYCLES_128K`"]
113    #[inline(always)]
114    pub fn is_cycles_128k(&self) -> bool {
115        *self == WDPL_A::CYCLES_128K
116    }
117    #[doc = "Checks if the value of the field is `CYCLES_256K`"]
118    #[inline(always)]
119    pub fn is_cycles_256k(&self) -> bool {
120        *self == WDPL_A::CYCLES_256K
121    }
122}
123#[doc = "Field `WDPL` writer - Watchdog Timer Prescaler - Low Bits"]
124pub type WDPL_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, WDTCSR_SPEC, u8, WDPL_A, 3, O>;
125impl<'a, const O: u8> WDPL_W<'a, O> {
126    #[doc = "- 2048 cycles, ~16ms/512K (524288) cycles, ~4s if WDPH is set"]
127    #[inline(always)]
128    pub fn cycles_2k_512k(self) -> &'a mut W {
129        self.variant(WDPL_A::CYCLES_2K_512K)
130    }
131    #[doc = "- 4096 cycles, ~32ms/1024K (1048576) cycles, ~8s if WDPH is set"]
132    #[inline(always)]
133    pub fn cycles_4k_1024k(self) -> &'a mut W {
134        self.variant(WDPL_A::CYCLES_4K_1024K)
135    }
136    #[doc = "- 8192 cycles, ~64ms"]
137    #[inline(always)]
138    pub fn cycles_8k(self) -> &'a mut W {
139        self.variant(WDPL_A::CYCLES_8K)
140    }
141    #[doc = "- 16K (16384) cycles, ~0.125s"]
142    #[inline(always)]
143    pub fn cycles_16k(self) -> &'a mut W {
144        self.variant(WDPL_A::CYCLES_16K)
145    }
146    #[doc = "- 32K (32768) cycles, ~0.25s"]
147    #[inline(always)]
148    pub fn cycles_32k(self) -> &'a mut W {
149        self.variant(WDPL_A::CYCLES_32K)
150    }
151    #[doc = "- 64K (65536) cycles, ~0.5s"]
152    #[inline(always)]
153    pub fn cycles_64k(self) -> &'a mut W {
154        self.variant(WDPL_A::CYCLES_64K)
155    }
156    #[doc = "- 128K (131072) cycles, ~1s"]
157    #[inline(always)]
158    pub fn cycles_128k(self) -> &'a mut W {
159        self.variant(WDPL_A::CYCLES_128K)
160    }
161    #[doc = "- 256K (262144) cycles, ~2s"]
162    #[inline(always)]
163    pub fn cycles_256k(self) -> &'a mut W {
164        self.variant(WDPL_A::CYCLES_256K)
165    }
166}
167#[doc = "Field `WDE` reader - Watch Dog Enable"]
168pub type WDE_R = crate::BitReader<bool>;
169#[doc = "Field `WDE` writer - Watch Dog Enable"]
170pub type WDE_W<'a, const O: u8> = crate::BitWriter<'a, u8, WDTCSR_SPEC, bool, O>;
171#[doc = "Field `WDCE` reader - Watchdog Change Enable"]
172pub type WDCE_R = crate::BitReader<bool>;
173#[doc = "Field `WDCE` writer - Watchdog Change Enable"]
174pub type WDCE_W<'a, const O: u8> = crate::BitWriter<'a, u8, WDTCSR_SPEC, bool, O>;
175#[doc = "Field `WDPH` reader - Watchdog Timer Prescaler - High Bit"]
176pub type WDPH_R = crate::BitReader<bool>;
177#[doc = "Field `WDPH` writer - Watchdog Timer Prescaler - High Bit"]
178pub type WDPH_W<'a, const O: u8> = crate::BitWriter<'a, u8, WDTCSR_SPEC, bool, O>;
179#[doc = "Field `WDIE` reader - Watchdog Timeout Interrupt Enable"]
180pub type WDIE_R = crate::BitReader<bool>;
181#[doc = "Field `WDIE` writer - Watchdog Timeout Interrupt Enable"]
182pub type WDIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, WDTCSR_SPEC, bool, O>;
183#[doc = "Field `WDIF` reader - Watchdog Timeout Interrupt Flag"]
184pub type WDIF_R = crate::BitReader<bool>;
185#[doc = "Field `WDIF` writer - Watchdog Timeout Interrupt Flag"]
186pub type WDIF_W<'a, const O: u8> = crate::BitWriter<'a, u8, WDTCSR_SPEC, bool, O>;
187impl R {
188    #[doc = "Bits 0:2 - Watchdog Timer Prescaler - Low Bits"]
189    #[inline(always)]
190    pub fn wdpl(&self) -> WDPL_R {
191        WDPL_R::new(self.bits & 7)
192    }
193    #[doc = "Bit 3 - Watch Dog Enable"]
194    #[inline(always)]
195    pub fn wde(&self) -> WDE_R {
196        WDE_R::new(((self.bits >> 3) & 1) != 0)
197    }
198    #[doc = "Bit 4 - Watchdog Change Enable"]
199    #[inline(always)]
200    pub fn wdce(&self) -> WDCE_R {
201        WDCE_R::new(((self.bits >> 4) & 1) != 0)
202    }
203    #[doc = "Bit 5 - Watchdog Timer Prescaler - High Bit"]
204    #[inline(always)]
205    pub fn wdph(&self) -> WDPH_R {
206        WDPH_R::new(((self.bits >> 5) & 1) != 0)
207    }
208    #[doc = "Bit 6 - Watchdog Timeout Interrupt Enable"]
209    #[inline(always)]
210    pub fn wdie(&self) -> WDIE_R {
211        WDIE_R::new(((self.bits >> 6) & 1) != 0)
212    }
213    #[doc = "Bit 7 - Watchdog Timeout Interrupt Flag"]
214    #[inline(always)]
215    pub fn wdif(&self) -> WDIF_R {
216        WDIF_R::new(((self.bits >> 7) & 1) != 0)
217    }
218}
219impl W {
220    #[doc = "Bits 0:2 - Watchdog Timer Prescaler - Low Bits"]
221    #[inline(always)]
222    #[must_use]
223    pub fn wdpl(&mut self) -> WDPL_W<0> {
224        WDPL_W::new(self)
225    }
226    #[doc = "Bit 3 - Watch Dog Enable"]
227    #[inline(always)]
228    #[must_use]
229    pub fn wde(&mut self) -> WDE_W<3> {
230        WDE_W::new(self)
231    }
232    #[doc = "Bit 4 - Watchdog Change Enable"]
233    #[inline(always)]
234    #[must_use]
235    pub fn wdce(&mut self) -> WDCE_W<4> {
236        WDCE_W::new(self)
237    }
238    #[doc = "Bit 5 - Watchdog Timer Prescaler - High Bit"]
239    #[inline(always)]
240    #[must_use]
241    pub fn wdph(&mut self) -> WDPH_W<5> {
242        WDPH_W::new(self)
243    }
244    #[doc = "Bit 6 - Watchdog Timeout Interrupt Enable"]
245    #[inline(always)]
246    #[must_use]
247    pub fn wdie(&mut self) -> WDIE_W<6> {
248        WDIE_W::new(self)
249    }
250    #[doc = "Bit 7 - Watchdog Timeout Interrupt Flag"]
251    #[inline(always)]
252    #[must_use]
253    pub fn wdif(&mut self) -> WDIF_W<7> {
254        WDIF_W::new(self)
255    }
256    #[doc = "Writes raw bits to the register."]
257    #[inline(always)]
258    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
259        self.0.bits(bits);
260        self
261    }
262}
263#[doc = "Watchdog Timer Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wdtcsr](index.html) module"]
264pub struct WDTCSR_SPEC;
265impl crate::RegisterSpec for WDTCSR_SPEC {
266    type Ux = u8;
267}
268#[doc = "`read()` method returns [wdtcsr::R](R) reader structure"]
269impl crate::Readable for WDTCSR_SPEC {
270    type Reader = R;
271}
272#[doc = "`write(|w| ..)` method takes [wdtcsr::W](W) writer structure"]
273impl crate::Writable for WDTCSR_SPEC {
274    type Writer = W;
275    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
276    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
277}
278#[doc = "`reset()` method sets WDTCSR to value 0"]
279impl crate::Resettable for WDTCSR_SPEC {
280    const RESET_VALUE: Self::Ux = 0;
281}
avr_device/devices/atmega2560/wdt/wdtcsr.rs

avr_device/devices/atmega2560/wdt/
wdtcsr.rs
