avr_device/devices/atmega328p/usart0/
ucsr0b.rs

1#[doc = "Register `UCSR0B` reader"]
2pub struct R(crate::R<UCSR0B_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UCSR0B_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UCSR0B_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UCSR0B_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `UCSR0B` writer"]
17pub struct W(crate::W<UCSR0B_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UCSR0B_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UCSR0B_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UCSR0B_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `TXB80` reader - Transmit Data Bit 8"]
38pub type TXB80_R = crate::BitReader<bool>;
39#[doc = "Field `TXB80` writer - Transmit Data Bit 8"]
40pub type TXB80_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
41#[doc = "Field `RXB80` reader - Receive Data Bit 8"]
42pub type RXB80_R = crate::BitReader<bool>;
43#[doc = "Field `UCSZ02` reader - Character Size"]
44pub type UCSZ02_R = crate::BitReader<bool>;
45#[doc = "Field `UCSZ02` writer - Character Size"]
46pub type UCSZ02_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
47#[doc = "Field `TXEN0` reader - Transmitter Enable"]
48pub type TXEN0_R = crate::BitReader<bool>;
49#[doc = "Field `TXEN0` writer - Transmitter Enable"]
50pub type TXEN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
51#[doc = "Field `RXEN0` reader - Receiver Enable"]
52pub type RXEN0_R = crate::BitReader<bool>;
53#[doc = "Field `RXEN0` writer - Receiver Enable"]
54pub type RXEN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
55#[doc = "Field `UDRIE0` reader - USART Data register Empty Interrupt Enable"]
56pub type UDRIE0_R = crate::BitReader<bool>;
57#[doc = "Field `UDRIE0` writer - USART Data register Empty Interrupt Enable"]
58pub type UDRIE0_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
59#[doc = "Field `TXCIE0` reader - TX Complete Interrupt Enable"]
60pub type TXCIE0_R = crate::BitReader<bool>;
61#[doc = "Field `TXCIE0` writer - TX Complete Interrupt Enable"]
62pub type TXCIE0_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
63#[doc = "Field `RXCIE0` reader - RX Complete Interrupt Enable"]
64pub type RXCIE0_R = crate::BitReader<bool>;
65#[doc = "Field `RXCIE0` writer - RX Complete Interrupt Enable"]
66pub type RXCIE0_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR0B_SPEC, bool, O>;
67impl R {
68    #[doc = "Bit 0 - Transmit Data Bit 8"]
69    #[inline(always)]
70    pub fn txb80(&self) -> TXB80_R {
71        TXB80_R::new((self.bits & 1) != 0)
72    }
73    #[doc = "Bit 1 - Receive Data Bit 8"]
74    #[inline(always)]
75    pub fn rxb80(&self) -> RXB80_R {
76        RXB80_R::new(((self.bits >> 1) & 1) != 0)
77    }
78    #[doc = "Bit 2 - Character Size"]
79    #[inline(always)]
80    pub fn ucsz02(&self) -> UCSZ02_R {
81        UCSZ02_R::new(((self.bits >> 2) & 1) != 0)
82    }
83    #[doc = "Bit 3 - Transmitter Enable"]
84    #[inline(always)]
85    pub fn txen0(&self) -> TXEN0_R {
86        TXEN0_R::new(((self.bits >> 3) & 1) != 0)
87    }
88    #[doc = "Bit 4 - Receiver Enable"]
89    #[inline(always)]
90    pub fn rxen0(&self) -> RXEN0_R {
91        RXEN0_R::new(((self.bits >> 4) & 1) != 0)
92    }
93    #[doc = "Bit 5 - USART Data register Empty Interrupt Enable"]
94    #[inline(always)]
95    pub fn udrie0(&self) -> UDRIE0_R {
96        UDRIE0_R::new(((self.bits >> 5) & 1) != 0)
97    }
98    #[doc = "Bit 6 - TX Complete Interrupt Enable"]
99    #[inline(always)]
100    pub fn txcie0(&self) -> TXCIE0_R {
101        TXCIE0_R::new(((self.bits >> 6) & 1) != 0)
102    }
103    #[doc = "Bit 7 - RX Complete Interrupt Enable"]
104    #[inline(always)]
105    pub fn rxcie0(&self) -> RXCIE0_R {
106        RXCIE0_R::new(((self.bits >> 7) & 1) != 0)
107    }
108}
109impl W {
110    #[doc = "Bit 0 - Transmit Data Bit 8"]
111    #[inline(always)]
112    #[must_use]
113    pub fn txb80(&mut self) -> TXB80_W<0> {
114        TXB80_W::new(self)
115    }
116    #[doc = "Bit 2 - Character Size"]
117    #[inline(always)]
118    #[must_use]
119    pub fn ucsz02(&mut self) -> UCSZ02_W<2> {
120        UCSZ02_W::new(self)
121    }
122    #[doc = "Bit 3 - Transmitter Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn txen0(&mut self) -> TXEN0_W<3> {
126        TXEN0_W::new(self)
127    }
128    #[doc = "Bit 4 - Receiver Enable"]
129    #[inline(always)]
130    #[must_use]
131    pub fn rxen0(&mut self) -> RXEN0_W<4> {
132        RXEN0_W::new(self)
133    }
134    #[doc = "Bit 5 - USART Data register Empty Interrupt Enable"]
135    #[inline(always)]
136    #[must_use]
137    pub fn udrie0(&mut self) -> UDRIE0_W<5> {
138        UDRIE0_W::new(self)
139    }
140    #[doc = "Bit 6 - TX Complete Interrupt Enable"]
141    #[inline(always)]
142    #[must_use]
143    pub fn txcie0(&mut self) -> TXCIE0_W<6> {
144        TXCIE0_W::new(self)
145    }
146    #[doc = "Bit 7 - RX Complete Interrupt Enable"]
147    #[inline(always)]
148    #[must_use]
149    pub fn rxcie0(&mut self) -> RXCIE0_W<7> {
150        RXCIE0_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "USART Control and Status Register B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucsr0b](index.html) module"]
160pub struct UCSR0B_SPEC;
161impl crate::RegisterSpec for UCSR0B_SPEC {
162    type Ux = u8;
163}
164#[doc = "`read()` method returns [ucsr0b::R](R) reader structure"]
165impl crate::Readable for UCSR0B_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [ucsr0b::W](W) writer structure"]
169impl crate::Writable for UCSR0B_SPEC {
170    type Writer = W;
171    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
173}
174#[doc = "`reset()` method sets UCSR0B to value 0"]
175impl crate::Resettable for UCSR0B_SPEC {
176    const RESET_VALUE: Self::Ux = 0;
177}
avr_device/devices/atmega328p/usart0/ucsr0b.rs

avr_device/devices/atmega328p/usart0/
ucsr0b.rs
