avr_device/devices/atmega32u4/pll/
pllfrq.rs

1#[doc = "Register `PLLFRQ` reader"]
2pub struct R(crate::R<PLLFRQ_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLLFRQ_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLLFRQ_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLLFRQ_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLLFRQ` writer"]
17pub struct W(crate::W<PLLFRQ_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLLFRQ_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLLFRQ_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLLFRQ_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PDIV` reader - PLL Lock Frequency"]
38pub type PDIV_R = crate::FieldReader<u8, PDIV_A>;
39#[doc = "PLL Lock Frequency\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum PDIV_A {
43    #[doc = "3: 40 MHz"]
44    MHZ40 = 3,
45    #[doc = "4: 48 MHz"]
46    MHZ48 = 4,
47    #[doc = "5: 56 MHz"]
48    MHZ56 = 5,
49    #[doc = "7: 72 MHz"]
50    MHZ72 = 7,
51    #[doc = "8: 80 MHz"]
52    MHZ80 = 8,
53    #[doc = "9: 88 MHz"]
54    MHZ88 = 9,
55    #[doc = "10: 96 MHz"]
56    MHZ96 = 10,
57}
58impl From<PDIV_A> for u8 {
59    #[inline(always)]
60    fn from(variant: PDIV_A) -> Self {
61        variant as _
62    }
63}
64impl PDIV_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<PDIV_A> {
68        match self.bits {
69            3 => Some(PDIV_A::MHZ40),
70            4 => Some(PDIV_A::MHZ48),
71            5 => Some(PDIV_A::MHZ56),
72            7 => Some(PDIV_A::MHZ72),
73            8 => Some(PDIV_A::MHZ80),
74            9 => Some(PDIV_A::MHZ88),
75            10 => Some(PDIV_A::MHZ96),
76            _ => None,
77        }
78    }
79    #[doc = "Checks if the value of the field is `MHZ40`"]
80    #[inline(always)]
81    pub fn is_mhz40(&self) -> bool {
82        *self == PDIV_A::MHZ40
83    }
84    #[doc = "Checks if the value of the field is `MHZ48`"]
85    #[inline(always)]
86    pub fn is_mhz48(&self) -> bool {
87        *self == PDIV_A::MHZ48
88    }
89    #[doc = "Checks if the value of the field is `MHZ56`"]
90    #[inline(always)]
91    pub fn is_mhz56(&self) -> bool {
92        *self == PDIV_A::MHZ56
93    }
94    #[doc = "Checks if the value of the field is `MHZ72`"]
95    #[inline(always)]
96    pub fn is_mhz72(&self) -> bool {
97        *self == PDIV_A::MHZ72
98    }
99    #[doc = "Checks if the value of the field is `MHZ80`"]
100    #[inline(always)]
101    pub fn is_mhz80(&self) -> bool {
102        *self == PDIV_A::MHZ80
103    }
104    #[doc = "Checks if the value of the field is `MHZ88`"]
105    #[inline(always)]
106    pub fn is_mhz88(&self) -> bool {
107        *self == PDIV_A::MHZ88
108    }
109    #[doc = "Checks if the value of the field is `MHZ96`"]
110    #[inline(always)]
111    pub fn is_mhz96(&self) -> bool {
112        *self == PDIV_A::MHZ96
113    }
114}
115#[doc = "Field `PDIV` writer - PLL Lock Frequency"]
116pub type PDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u8, PLLFRQ_SPEC, u8, PDIV_A, 4, O>;
117impl<'a, const O: u8> PDIV_W<'a, O> {
118    #[doc = "40 MHz"]
119    #[inline(always)]
120    pub fn mhz40(self) -> &'a mut W {
121        self.variant(PDIV_A::MHZ40)
122    }
123    #[doc = "48 MHz"]
124    #[inline(always)]
125    pub fn mhz48(self) -> &'a mut W {
126        self.variant(PDIV_A::MHZ48)
127    }
128    #[doc = "56 MHz"]
129    #[inline(always)]
130    pub fn mhz56(self) -> &'a mut W {
131        self.variant(PDIV_A::MHZ56)
132    }
133    #[doc = "72 MHz"]
134    #[inline(always)]
135    pub fn mhz72(self) -> &'a mut W {
136        self.variant(PDIV_A::MHZ72)
137    }
138    #[doc = "80 MHz"]
139    #[inline(always)]
140    pub fn mhz80(self) -> &'a mut W {
141        self.variant(PDIV_A::MHZ80)
142    }
143    #[doc = "88 MHz"]
144    #[inline(always)]
145    pub fn mhz88(self) -> &'a mut W {
146        self.variant(PDIV_A::MHZ88)
147    }
148    #[doc = "96 MHz"]
149    #[inline(always)]
150    pub fn mhz96(self) -> &'a mut W {
151        self.variant(PDIV_A::MHZ96)
152    }
153}
154#[doc = "Field `PLLTM` reader - PLL Postscaler for High Speed Timer"]
155pub type PLLTM_R = crate::FieldReader<u8, PLLTM_A>;
156#[doc = "PLL Postscaler for High Speed Timer\n\nValue on reset: 0"]
157#[derive(Clone, Copy, Debug, PartialEq, Eq)]
158#[repr(u8)]
159pub enum PLLTM_A {
160    #[doc = "0: 0 (Disconnected)"]
161    DISCONNECTED = 0,
162    #[doc = "1: 1"]
163    FACTOR_1 = 1,
164    #[doc = "2: 1.5"]
165    FACTOR_15 = 2,
166    #[doc = "3: 2"]
167    FACTOR_2 = 3,
168}
169impl From<PLLTM_A> for u8 {
170    #[inline(always)]
171    fn from(variant: PLLTM_A) -> Self {
172        variant as _
173    }
174}
175impl PLLTM_R {
176    #[doc = "Get enumerated values variant"]
177    #[inline(always)]
178    pub fn variant(&self) -> PLLTM_A {
179        match self.bits {
180            0 => PLLTM_A::DISCONNECTED,
181            1 => PLLTM_A::FACTOR_1,
182            2 => PLLTM_A::FACTOR_15,
183            3 => PLLTM_A::FACTOR_2,
184            _ => unreachable!(),
185        }
186    }
187    #[doc = "Checks if the value of the field is `DISCONNECTED`"]
188    #[inline(always)]
189    pub fn is_disconnected(&self) -> bool {
190        *self == PLLTM_A::DISCONNECTED
191    }
192    #[doc = "Checks if the value of the field is `FACTOR_1`"]
193    #[inline(always)]
194    pub fn is_factor_1(&self) -> bool {
195        *self == PLLTM_A::FACTOR_1
196    }
197    #[doc = "Checks if the value of the field is `FACTOR_15`"]
198    #[inline(always)]
199    pub fn is_factor_15(&self) -> bool {
200        *self == PLLTM_A::FACTOR_15
201    }
202    #[doc = "Checks if the value of the field is `FACTOR_2`"]
203    #[inline(always)]
204    pub fn is_factor_2(&self) -> bool {
205        *self == PLLTM_A::FACTOR_2
206    }
207}
208#[doc = "Field `PLLTM` writer - PLL Postscaler for High Speed Timer"]
209pub type PLLTM_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, PLLFRQ_SPEC, u8, PLLTM_A, 2, O>;
210impl<'a, const O: u8> PLLTM_W<'a, O> {
211    #[doc = "0 (Disconnected)"]
212    #[inline(always)]
213    pub fn disconnected(self) -> &'a mut W {
214        self.variant(PLLTM_A::DISCONNECTED)
215    }
216    #[doc = "1"]
217    #[inline(always)]
218    pub fn factor_1(self) -> &'a mut W {
219        self.variant(PLLTM_A::FACTOR_1)
220    }
221    #[doc = "1.5"]
222    #[inline(always)]
223    pub fn factor_15(self) -> &'a mut W {
224        self.variant(PLLTM_A::FACTOR_15)
225    }
226    #[doc = "2"]
227    #[inline(always)]
228    pub fn factor_2(self) -> &'a mut W {
229        self.variant(PLLTM_A::FACTOR_2)
230    }
231}
232#[doc = "Field `PLLUSB` reader - PLL Postscaler for USB Peripheral"]
233pub type PLLUSB_R = crate::BitReader<bool>;
234#[doc = "Field `PLLUSB` writer - PLL Postscaler for USB Peripheral"]
235pub type PLLUSB_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLFRQ_SPEC, bool, O>;
236#[doc = "Field `PINMUX` reader - PLL Input Multiplexer"]
237pub type PINMUX_R = crate::BitReader<bool>;
238#[doc = "Field `PINMUX` writer - PLL Input Multiplexer"]
239pub type PINMUX_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLFRQ_SPEC, bool, O>;
240impl R {
241    #[doc = "Bits 0:3 - PLL Lock Frequency"]
242    #[inline(always)]
243    pub fn pdiv(&self) -> PDIV_R {
244        PDIV_R::new(self.bits & 0x0f)
245    }
246    #[doc = "Bits 4:5 - PLL Postscaler for High Speed Timer"]
247    #[inline(always)]
248    pub fn plltm(&self) -> PLLTM_R {
249        PLLTM_R::new((self.bits >> 4) & 3)
250    }
251    #[doc = "Bit 6 - PLL Postscaler for USB Peripheral"]
252    #[inline(always)]
253    pub fn pllusb(&self) -> PLLUSB_R {
254        PLLUSB_R::new(((self.bits >> 6) & 1) != 0)
255    }
256    #[doc = "Bit 7 - PLL Input Multiplexer"]
257    #[inline(always)]
258    pub fn pinmux(&self) -> PINMUX_R {
259        PINMUX_R::new(((self.bits >> 7) & 1) != 0)
260    }
261}
262impl W {
263    #[doc = "Bits 0:3 - PLL Lock Frequency"]
264    #[inline(always)]
265    #[must_use]
266    pub fn pdiv(&mut self) -> PDIV_W<0> {
267        PDIV_W::new(self)
268    }
269    #[doc = "Bits 4:5 - PLL Postscaler for High Speed Timer"]
270    #[inline(always)]
271    #[must_use]
272    pub fn plltm(&mut self) -> PLLTM_W<4> {
273        PLLTM_W::new(self)
274    }
275    #[doc = "Bit 6 - PLL Postscaler for USB Peripheral"]
276    #[inline(always)]
277    #[must_use]
278    pub fn pllusb(&mut self) -> PLLUSB_W<6> {
279        PLLUSB_W::new(self)
280    }
281    #[doc = "Bit 7 - PLL Input Multiplexer"]
282    #[inline(always)]
283    #[must_use]
284    pub fn pinmux(&mut self) -> PINMUX_W<7> {
285        PINMUX_W::new(self)
286    }
287    #[doc = "Writes raw bits to the register."]
288    #[inline(always)]
289    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
290        self.0.bits(bits);
291        self
292    }
293}
294#[doc = "PLL Frequency Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pllfrq](index.html) module"]
295pub struct PLLFRQ_SPEC;
296impl crate::RegisterSpec for PLLFRQ_SPEC {
297    type Ux = u8;
298}
299#[doc = "`read()` method returns [pllfrq::R](R) reader structure"]
300impl crate::Readable for PLLFRQ_SPEC {
301    type Reader = R;
302}
303#[doc = "`write(|w| ..)` method takes [pllfrq::W](W) writer structure"]
304impl crate::Writable for PLLFRQ_SPEC {
305    type Writer = W;
306    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
307    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
308}
309#[doc = "`reset()` method sets PLLFRQ to value 0"]
310impl crate::Resettable for PLLFRQ_SPEC {
311    const RESET_VALUE: Self::Ux = 0;
312}
avr_device/devices/atmega32u4/pll/pllfrq.rs

avr_device/devices/atmega32u4/pll/
pllfrq.rs
