avr_device/devices/atmega4809/ac0/
muxctrla.rs1#[doc = "Register `MUXCTRLA` reader"]
2pub struct R(crate::R<MUXCTRLA_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<MUXCTRLA_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<MUXCTRLA_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<MUXCTRLA_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `MUXCTRLA` writer"]
17pub struct W(crate::W<MUXCTRLA_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<MUXCTRLA_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<MUXCTRLA_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<MUXCTRLA_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `MUXNEG` reader - Negative Input MUX Selection"]
38pub type MUXNEG_R = crate::FieldReader<u8, MUXNEG_A>;
39#[doc = "Negative Input MUX Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MUXNEG_A {
43 #[doc = "0: Negative Pin 0"]
44 PIN0 = 0,
45 #[doc = "1: Negative Pin 1"]
46 PIN1 = 1,
47 #[doc = "2: Negative Pin 2"]
48 PIN2 = 2,
49 #[doc = "3: DAC Voltage Reference"]
50 DACREF = 3,
51}
52impl From<MUXNEG_A> for u8 {
53 #[inline(always)]
54 fn from(variant: MUXNEG_A) -> Self {
55 variant as _
56 }
57}
58impl MUXNEG_R {
59 #[doc = "Get enumerated values variant"]
60 #[inline(always)]
61 pub fn variant(&self) -> MUXNEG_A {
62 match self.bits {
63 0 => MUXNEG_A::PIN0,
64 1 => MUXNEG_A::PIN1,
65 2 => MUXNEG_A::PIN2,
66 3 => MUXNEG_A::DACREF,
67 _ => unreachable!(),
68 }
69 }
70 #[doc = "Checks if the value of the field is `PIN0`"]
71 #[inline(always)]
72 pub fn is_pin0(&self) -> bool {
73 *self == MUXNEG_A::PIN0
74 }
75 #[doc = "Checks if the value of the field is `PIN1`"]
76 #[inline(always)]
77 pub fn is_pin1(&self) -> bool {
78 *self == MUXNEG_A::PIN1
79 }
80 #[doc = "Checks if the value of the field is `PIN2`"]
81 #[inline(always)]
82 pub fn is_pin2(&self) -> bool {
83 *self == MUXNEG_A::PIN2
84 }
85 #[doc = "Checks if the value of the field is `DACREF`"]
86 #[inline(always)]
87 pub fn is_dacref(&self) -> bool {
88 *self == MUXNEG_A::DACREF
89 }
90}
91#[doc = "Field `MUXNEG` writer - Negative Input MUX Selection"]
92pub type MUXNEG_W<'a, const O: u8> =
93 crate::FieldWriterSafe<'a, u8, MUXCTRLA_SPEC, u8, MUXNEG_A, 2, O>;
94impl<'a, const O: u8> MUXNEG_W<'a, O> {
95 #[doc = "Negative Pin 0"]
96 #[inline(always)]
97 pub fn pin0(self) -> &'a mut W {
98 self.variant(MUXNEG_A::PIN0)
99 }
100 #[doc = "Negative Pin 1"]
101 #[inline(always)]
102 pub fn pin1(self) -> &'a mut W {
103 self.variant(MUXNEG_A::PIN1)
104 }
105 #[doc = "Negative Pin 2"]
106 #[inline(always)]
107 pub fn pin2(self) -> &'a mut W {
108 self.variant(MUXNEG_A::PIN2)
109 }
110 #[doc = "DAC Voltage Reference"]
111 #[inline(always)]
112 pub fn dacref(self) -> &'a mut W {
113 self.variant(MUXNEG_A::DACREF)
114 }
115}
116#[doc = "Field `MUXPOS` reader - Positive Input MUX Selection"]
117pub type MUXPOS_R = crate::FieldReader<u8, MUXPOS_A>;
118#[doc = "Positive Input MUX Selection\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120#[repr(u8)]
121pub enum MUXPOS_A {
122 #[doc = "0: Positive Pin 0"]
123 PIN0 = 0,
124 #[doc = "1: Positive Pin 1"]
125 PIN1 = 1,
126 #[doc = "2: Positive Pin 2"]
127 PIN2 = 2,
128 #[doc = "3: Positive Pin 3"]
129 PIN3 = 3,
130}
131impl From<MUXPOS_A> for u8 {
132 #[inline(always)]
133 fn from(variant: MUXPOS_A) -> Self {
134 variant as _
135 }
136}
137impl MUXPOS_R {
138 #[doc = "Get enumerated values variant"]
139 #[inline(always)]
140 pub fn variant(&self) -> MUXPOS_A {
141 match self.bits {
142 0 => MUXPOS_A::PIN0,
143 1 => MUXPOS_A::PIN1,
144 2 => MUXPOS_A::PIN2,
145 3 => MUXPOS_A::PIN3,
146 _ => unreachable!(),
147 }
148 }
149 #[doc = "Checks if the value of the field is `PIN0`"]
150 #[inline(always)]
151 pub fn is_pin0(&self) -> bool {
152 *self == MUXPOS_A::PIN0
153 }
154 #[doc = "Checks if the value of the field is `PIN1`"]
155 #[inline(always)]
156 pub fn is_pin1(&self) -> bool {
157 *self == MUXPOS_A::PIN1
158 }
159 #[doc = "Checks if the value of the field is `PIN2`"]
160 #[inline(always)]
161 pub fn is_pin2(&self) -> bool {
162 *self == MUXPOS_A::PIN2
163 }
164 #[doc = "Checks if the value of the field is `PIN3`"]
165 #[inline(always)]
166 pub fn is_pin3(&self) -> bool {
167 *self == MUXPOS_A::PIN3
168 }
169}
170#[doc = "Field `MUXPOS` writer - Positive Input MUX Selection"]
171pub type MUXPOS_W<'a, const O: u8> =
172 crate::FieldWriterSafe<'a, u8, MUXCTRLA_SPEC, u8, MUXPOS_A, 2, O>;
173impl<'a, const O: u8> MUXPOS_W<'a, O> {
174 #[doc = "Positive Pin 0"]
175 #[inline(always)]
176 pub fn pin0(self) -> &'a mut W {
177 self.variant(MUXPOS_A::PIN0)
178 }
179 #[doc = "Positive Pin 1"]
180 #[inline(always)]
181 pub fn pin1(self) -> &'a mut W {
182 self.variant(MUXPOS_A::PIN1)
183 }
184 #[doc = "Positive Pin 2"]
185 #[inline(always)]
186 pub fn pin2(self) -> &'a mut W {
187 self.variant(MUXPOS_A::PIN2)
188 }
189 #[doc = "Positive Pin 3"]
190 #[inline(always)]
191 pub fn pin3(self) -> &'a mut W {
192 self.variant(MUXPOS_A::PIN3)
193 }
194}
195#[doc = "Field `INVERT` reader - Invert AC Output"]
196pub type INVERT_R = crate::BitReader<bool>;
197#[doc = "Field `INVERT` writer - Invert AC Output"]
198pub type INVERT_W<'a, const O: u8> = crate::BitWriter<'a, u8, MUXCTRLA_SPEC, bool, O>;
199impl R {
200 #[doc = "Bits 0:1 - Negative Input MUX Selection"]
201 #[inline(always)]
202 pub fn muxneg(&self) -> MUXNEG_R {
203 MUXNEG_R::new(self.bits & 3)
204 }
205 #[doc = "Bits 3:4 - Positive Input MUX Selection"]
206 #[inline(always)]
207 pub fn muxpos(&self) -> MUXPOS_R {
208 MUXPOS_R::new((self.bits >> 3) & 3)
209 }
210 #[doc = "Bit 7 - Invert AC Output"]
211 #[inline(always)]
212 pub fn invert(&self) -> INVERT_R {
213 INVERT_R::new(((self.bits >> 7) & 1) != 0)
214 }
215}
216impl W {
217 #[doc = "Bits 0:1 - Negative Input MUX Selection"]
218 #[inline(always)]
219 #[must_use]
220 pub fn muxneg(&mut self) -> MUXNEG_W<0> {
221 MUXNEG_W::new(self)
222 }
223 #[doc = "Bits 3:4 - Positive Input MUX Selection"]
224 #[inline(always)]
225 #[must_use]
226 pub fn muxpos(&mut self) -> MUXPOS_W<3> {
227 MUXPOS_W::new(self)
228 }
229 #[doc = "Bit 7 - Invert AC Output"]
230 #[inline(always)]
231 #[must_use]
232 pub fn invert(&mut self) -> INVERT_W<7> {
233 INVERT_W::new(self)
234 }
235 #[doc = "Writes raw bits to the register."]
236 #[inline(always)]
237 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
238 self.0.bits(bits);
239 self
240 }
241}
242#[doc = "Mux Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [muxctrla](index.html) module"]
243pub struct MUXCTRLA_SPEC;
244impl crate::RegisterSpec for MUXCTRLA_SPEC {
245 type Ux = u8;
246}
247#[doc = "`read()` method returns [muxctrla::R](R) reader structure"]
248impl crate::Readable for MUXCTRLA_SPEC {
249 type Reader = R;
250}
251#[doc = "`write(|w| ..)` method takes [muxctrla::W](W) writer structure"]
252impl crate::Writable for MUXCTRLA_SPEC {
253 type Writer = W;
254 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
255 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
256}
257#[doc = "`reset()` method sets MUXCTRLA to value 0"]
258impl crate::Resettable for MUXCTRLA_SPEC {
259 const RESET_VALUE: Self::Ux = 0;
260}