avr_device/devices/atmega4809/ccl/
seqctrl0.rs

1#[doc = "Register `SEQCTRL0` reader"]
2pub struct R(crate::R<SEQCTRL0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SEQCTRL0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SEQCTRL0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SEQCTRL0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SEQCTRL0` writer"]
17pub struct W(crate::W<SEQCTRL0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SEQCTRL0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SEQCTRL0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SEQCTRL0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SEQSEL0` reader - Sequential Selection"]
38pub type SEQSEL0_R = crate::FieldReader<u8, SEQSEL0_A>;
39#[doc = "Sequential Selection\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SEQSEL0_A {
43    #[doc = "0: Sequential logic disabled"]
44    DISABLE = 0,
45    #[doc = "1: D FlipFlop"]
46    DFF = 1,
47    #[doc = "2: JK FlipFlop"]
48    JK = 2,
49    #[doc = "3: D Latch"]
50    LATCH = 3,
51    #[doc = "4: RS Latch"]
52    RS = 4,
53}
54impl From<SEQSEL0_A> for u8 {
55    #[inline(always)]
56    fn from(variant: SEQSEL0_A) -> Self {
57        variant as _
58    }
59}
60impl SEQSEL0_R {
61    #[doc = "Get enumerated values variant"]
62    #[inline(always)]
63    pub fn variant(&self) -> Option<SEQSEL0_A> {
64        match self.bits {
65            0 => Some(SEQSEL0_A::DISABLE),
66            1 => Some(SEQSEL0_A::DFF),
67            2 => Some(SEQSEL0_A::JK),
68            3 => Some(SEQSEL0_A::LATCH),
69            4 => Some(SEQSEL0_A::RS),
70            _ => None,
71        }
72    }
73    #[doc = "Checks if the value of the field is `DISABLE`"]
74    #[inline(always)]
75    pub fn is_disable(&self) -> bool {
76        *self == SEQSEL0_A::DISABLE
77    }
78    #[doc = "Checks if the value of the field is `DFF`"]
79    #[inline(always)]
80    pub fn is_dff(&self) -> bool {
81        *self == SEQSEL0_A::DFF
82    }
83    #[doc = "Checks if the value of the field is `JK`"]
84    #[inline(always)]
85    pub fn is_jk(&self) -> bool {
86        *self == SEQSEL0_A::JK
87    }
88    #[doc = "Checks if the value of the field is `LATCH`"]
89    #[inline(always)]
90    pub fn is_latch(&self) -> bool {
91        *self == SEQSEL0_A::LATCH
92    }
93    #[doc = "Checks if the value of the field is `RS`"]
94    #[inline(always)]
95    pub fn is_rs(&self) -> bool {
96        *self == SEQSEL0_A::RS
97    }
98}
99#[doc = "Field `SEQSEL0` writer - Sequential Selection"]
100pub type SEQSEL0_W<'a, const O: u8> =
101    crate::FieldWriter<'a, u8, SEQCTRL0_SPEC, u8, SEQSEL0_A, 3, O>;
102impl<'a, const O: u8> SEQSEL0_W<'a, O> {
103    #[doc = "Sequential logic disabled"]
104    #[inline(always)]
105    pub fn disable(self) -> &'a mut W {
106        self.variant(SEQSEL0_A::DISABLE)
107    }
108    #[doc = "D FlipFlop"]
109    #[inline(always)]
110    pub fn dff(self) -> &'a mut W {
111        self.variant(SEQSEL0_A::DFF)
112    }
113    #[doc = "JK FlipFlop"]
114    #[inline(always)]
115    pub fn jk(self) -> &'a mut W {
116        self.variant(SEQSEL0_A::JK)
117    }
118    #[doc = "D Latch"]
119    #[inline(always)]
120    pub fn latch(self) -> &'a mut W {
121        self.variant(SEQSEL0_A::LATCH)
122    }
123    #[doc = "RS Latch"]
124    #[inline(always)]
125    pub fn rs(self) -> &'a mut W {
126        self.variant(SEQSEL0_A::RS)
127    }
128}
129impl R {
130    #[doc = "Bits 0:2 - Sequential Selection"]
131    #[inline(always)]
132    pub fn seqsel0(&self) -> SEQSEL0_R {
133        SEQSEL0_R::new(self.bits & 7)
134    }
135}
136impl W {
137    #[doc = "Bits 0:2 - Sequential Selection"]
138    #[inline(always)]
139    #[must_use]
140    pub fn seqsel0(&mut self) -> SEQSEL0_W<0> {
141        SEQSEL0_W::new(self)
142    }
143    #[doc = "Writes raw bits to the register."]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
146        self.0.bits(bits);
147        self
148    }
149}
150#[doc = "Sequential Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl0](index.html) module"]
151pub struct SEQCTRL0_SPEC;
152impl crate::RegisterSpec for SEQCTRL0_SPEC {
153    type Ux = u8;
154}
155#[doc = "`read()` method returns [seqctrl0::R](R) reader structure"]
156impl crate::Readable for SEQCTRL0_SPEC {
157    type Reader = R;
158}
159#[doc = "`write(|w| ..)` method takes [seqctrl0::W](W) writer structure"]
160impl crate::Writable for SEQCTRL0_SPEC {
161    type Writer = W;
162    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
163    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
164}
165#[doc = "`reset()` method sets SEQCTRL0 to value 0"]
166impl crate::Resettable for SEQCTRL0_SPEC {
167    const RESET_VALUE: Self::Ux = 0;
168}
avr_device/devices/atmega4809/ccl/seqctrl0.rs

avr_device/devices/atmega4809/ccl/
seqctrl0.rs
