avr_device/devices/atmega4809/clkctrl/
mclkctrla.rs

1#[doc = "Register `MCLKCTRLA` reader"]
2pub struct R(crate::R<MCLKCTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MCLKCTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MCLKCTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MCLKCTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MCLKCTRLA` writer"]
17pub struct W(crate::W<MCLKCTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MCLKCTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MCLKCTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MCLKCTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLKSEL` reader - clock select"]
38pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
39#[doc = "clock select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CLKSEL_A {
43    #[doc = "0: 20MHz oscillator"]
44    OSC20M = 0,
45    #[doc = "1: 32KHz oscillator"]
46    OSCULP32K = 1,
47    #[doc = "2: 32.768kHz crystal oscillator"]
48    XOSC32K = 2,
49    #[doc = "3: External clock"]
50    EXTCLK = 3,
51}
52impl From<CLKSEL_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CLKSEL_A) -> Self {
55        variant as _
56    }
57}
58impl CLKSEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> CLKSEL_A {
62        match self.bits {
63            0 => CLKSEL_A::OSC20M,
64            1 => CLKSEL_A::OSCULP32K,
65            2 => CLKSEL_A::XOSC32K,
66            3 => CLKSEL_A::EXTCLK,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `OSC20M`"]
71    #[inline(always)]
72    pub fn is_osc20m(&self) -> bool {
73        *self == CLKSEL_A::OSC20M
74    }
75    #[doc = "Checks if the value of the field is `OSCULP32K`"]
76    #[inline(always)]
77    pub fn is_osculp32k(&self) -> bool {
78        *self == CLKSEL_A::OSCULP32K
79    }
80    #[doc = "Checks if the value of the field is `XOSC32K`"]
81    #[inline(always)]
82    pub fn is_xosc32k(&self) -> bool {
83        *self == CLKSEL_A::XOSC32K
84    }
85    #[doc = "Checks if the value of the field is `EXTCLK`"]
86    #[inline(always)]
87    pub fn is_extclk(&self) -> bool {
88        *self == CLKSEL_A::EXTCLK
89    }
90}
91#[doc = "Field `CLKSEL` writer - clock select"]
92pub type CLKSEL_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u8, MCLKCTRLA_SPEC, u8, CLKSEL_A, 2, O>;
94impl<'a, const O: u8> CLKSEL_W<'a, O> {
95    #[doc = "20MHz oscillator"]
96    #[inline(always)]
97    pub fn osc20m(self) -> &'a mut W {
98        self.variant(CLKSEL_A::OSC20M)
99    }
100    #[doc = "32KHz oscillator"]
101    #[inline(always)]
102    pub fn osculp32k(self) -> &'a mut W {
103        self.variant(CLKSEL_A::OSCULP32K)
104    }
105    #[doc = "32.768kHz crystal oscillator"]
106    #[inline(always)]
107    pub fn xosc32k(self) -> &'a mut W {
108        self.variant(CLKSEL_A::XOSC32K)
109    }
110    #[doc = "External clock"]
111    #[inline(always)]
112    pub fn extclk(self) -> &'a mut W {
113        self.variant(CLKSEL_A::EXTCLK)
114    }
115}
116#[doc = "Field `CLKOUT` reader - System clock out"]
117pub type CLKOUT_R = crate::BitReader<bool>;
118#[doc = "Field `CLKOUT` writer - System clock out"]
119pub type CLKOUT_W<'a, const O: u8> = crate::BitWriter<'a, u8, MCLKCTRLA_SPEC, bool, O>;
120impl R {
121    #[doc = "Bits 0:1 - clock select"]
122    #[inline(always)]
123    pub fn clksel(&self) -> CLKSEL_R {
124        CLKSEL_R::new(self.bits & 3)
125    }
126    #[doc = "Bit 7 - System clock out"]
127    #[inline(always)]
128    pub fn clkout(&self) -> CLKOUT_R {
129        CLKOUT_R::new(((self.bits >> 7) & 1) != 0)
130    }
131}
132impl W {
133    #[doc = "Bits 0:1 - clock select"]
134    #[inline(always)]
135    #[must_use]
136    pub fn clksel(&mut self) -> CLKSEL_W<0> {
137        CLKSEL_W::new(self)
138    }
139    #[doc = "Bit 7 - System clock out"]
140    #[inline(always)]
141    #[must_use]
142    pub fn clkout(&mut self) -> CLKOUT_W<7> {
143        CLKOUT_W::new(self)
144    }
145    #[doc = "Writes raw bits to the register."]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
148        self.0.bits(bits);
149        self
150    }
151}
152#[doc = "MCLK Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mclkctrla](index.html) module"]
153pub struct MCLKCTRLA_SPEC;
154impl crate::RegisterSpec for MCLKCTRLA_SPEC {
155    type Ux = u8;
156}
157#[doc = "`read()` method returns [mclkctrla::R](R) reader structure"]
158impl crate::Readable for MCLKCTRLA_SPEC {
159    type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [mclkctrla::W](W) writer structure"]
162impl crate::Writable for MCLKCTRLA_SPEC {
163    type Writer = W;
164    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets MCLKCTRLA to value 0"]
168impl crate::Resettable for MCLKCTRLA_SPEC {
169    const RESET_VALUE: Self::Ux = 0;
170}
avr_device/devices/atmega4809/clkctrl/mclkctrla.rs

avr_device/devices/atmega4809/clkctrl/
mclkctrla.rs
