avr_device/devices/atmega4809/spi0/
intctrl.rs

1#[doc = "Register `INTCTRL` reader"]
2pub struct R(crate::R<INTCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTCTRL` writer"]
17pub struct W(crate::W<INTCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `IE` reader - Interrupt Enable"]
38pub type IE_R = crate::BitReader<bool>;
39#[doc = "Field `IE` writer - Interrupt Enable"]
40pub type IE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTCTRL_SPEC, bool, O>;
41#[doc = "Field `SSIE` reader - Slave Select Trigger Interrupt Enable"]
42pub type SSIE_R = crate::BitReader<bool>;
43#[doc = "Field `SSIE` writer - Slave Select Trigger Interrupt Enable"]
44pub type SSIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTCTRL_SPEC, bool, O>;
45#[doc = "Field `DREIE` reader - Data Register Empty Interrupt Enable"]
46pub type DREIE_R = crate::BitReader<bool>;
47#[doc = "Field `DREIE` writer - Data Register Empty Interrupt Enable"]
48pub type DREIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTCTRL_SPEC, bool, O>;
49#[doc = "Field `TXCIE` reader - Transfer Complete Interrupt Enable"]
50pub type TXCIE_R = crate::BitReader<bool>;
51#[doc = "Field `TXCIE` writer - Transfer Complete Interrupt Enable"]
52pub type TXCIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTCTRL_SPEC, bool, O>;
53#[doc = "Field `RXCIE` reader - Receive Complete Interrupt Enable"]
54pub type RXCIE_R = crate::BitReader<bool>;
55#[doc = "Field `RXCIE` writer - Receive Complete Interrupt Enable"]
56pub type RXCIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTCTRL_SPEC, bool, O>;
57impl R {
58    #[doc = "Bit 0 - Interrupt Enable"]
59    #[inline(always)]
60    pub fn ie(&self) -> IE_R {
61        IE_R::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 4 - Slave Select Trigger Interrupt Enable"]
64    #[inline(always)]
65    pub fn ssie(&self) -> SSIE_R {
66        SSIE_R::new(((self.bits >> 4) & 1) != 0)
67    }
68    #[doc = "Bit 5 - Data Register Empty Interrupt Enable"]
69    #[inline(always)]
70    pub fn dreie(&self) -> DREIE_R {
71        DREIE_R::new(((self.bits >> 5) & 1) != 0)
72    }
73    #[doc = "Bit 6 - Transfer Complete Interrupt Enable"]
74    #[inline(always)]
75    pub fn txcie(&self) -> TXCIE_R {
76        TXCIE_R::new(((self.bits >> 6) & 1) != 0)
77    }
78    #[doc = "Bit 7 - Receive Complete Interrupt Enable"]
79    #[inline(always)]
80    pub fn rxcie(&self) -> RXCIE_R {
81        RXCIE_R::new(((self.bits >> 7) & 1) != 0)
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Interrupt Enable"]
86    #[inline(always)]
87    #[must_use]
88    pub fn ie(&mut self) -> IE_W<0> {
89        IE_W::new(self)
90    }
91    #[doc = "Bit 4 - Slave Select Trigger Interrupt Enable"]
92    #[inline(always)]
93    #[must_use]
94    pub fn ssie(&mut self) -> SSIE_W<4> {
95        SSIE_W::new(self)
96    }
97    #[doc = "Bit 5 - Data Register Empty Interrupt Enable"]
98    #[inline(always)]
99    #[must_use]
100    pub fn dreie(&mut self) -> DREIE_W<5> {
101        DREIE_W::new(self)
102    }
103    #[doc = "Bit 6 - Transfer Complete Interrupt Enable"]
104    #[inline(always)]
105    #[must_use]
106    pub fn txcie(&mut self) -> TXCIE_W<6> {
107        TXCIE_W::new(self)
108    }
109    #[doc = "Bit 7 - Receive Complete Interrupt Enable"]
110    #[inline(always)]
111    #[must_use]
112    pub fn rxcie(&mut self) -> RXCIE_W<7> {
113        RXCIE_W::new(self)
114    }
115    #[doc = "Writes raw bits to the register."]
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122#[doc = "Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intctrl](index.html) module"]
123pub struct INTCTRL_SPEC;
124impl crate::RegisterSpec for INTCTRL_SPEC {
125    type Ux = u8;
126}
127#[doc = "`read()` method returns [intctrl::R](R) reader structure"]
128impl crate::Readable for INTCTRL_SPEC {
129    type Reader = R;
130}
131#[doc = "`write(|w| ..)` method takes [intctrl::W](W) writer structure"]
132impl crate::Writable for INTCTRL_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets INTCTRL to value 0"]
138impl crate::Resettable for INTCTRL_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
avr_device/devices/atmega4809/spi0/intctrl.rs

avr_device/devices/atmega4809/spi0/
intctrl.rs
