avr_device/devices/attiny85/cpu/
pllcsr.rs

1#[doc = "Register `PLLCSR` reader"]
2pub struct R(crate::R<PLLCSR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PLLCSR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PLLCSR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PLLCSR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PLLCSR` writer"]
17pub struct W(crate::W<PLLCSR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PLLCSR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PLLCSR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PLLCSR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PLOCK` reader - PLL Lock detector"]
38pub type PLOCK_R = crate::BitReader<bool>;
39#[doc = "Field `PLLE` reader - PLL Enable"]
40pub type PLLE_R = crate::BitReader<bool>;
41#[doc = "Field `PLLE` writer - PLL Enable"]
42pub type PLLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLCSR_SPEC, bool, O>;
43#[doc = "Field `PCKE` reader - PCK Enable"]
44pub type PCKE_R = crate::BitReader<bool>;
45#[doc = "Field `PCKE` writer - PCK Enable"]
46pub type PCKE_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLCSR_SPEC, bool, O>;
47#[doc = "Field `LSM` reader - Low speed mode"]
48pub type LSM_R = crate::BitReader<bool>;
49#[doc = "Field `LSM` writer - Low speed mode"]
50pub type LSM_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLLCSR_SPEC, bool, O>;
51impl R {
52    #[doc = "Bit 0 - PLL Lock detector"]
53    #[inline(always)]
54    pub fn plock(&self) -> PLOCK_R {
55        PLOCK_R::new((self.bits & 1) != 0)
56    }
57    #[doc = "Bit 1 - PLL Enable"]
58    #[inline(always)]
59    pub fn plle(&self) -> PLLE_R {
60        PLLE_R::new(((self.bits >> 1) & 1) != 0)
61    }
62    #[doc = "Bit 2 - PCK Enable"]
63    #[inline(always)]
64    pub fn pcke(&self) -> PCKE_R {
65        PCKE_R::new(((self.bits >> 2) & 1) != 0)
66    }
67    #[doc = "Bit 7 - Low speed mode"]
68    #[inline(always)]
69    pub fn lsm(&self) -> LSM_R {
70        LSM_R::new(((self.bits >> 7) & 1) != 0)
71    }
72}
73impl W {
74    #[doc = "Bit 1 - PLL Enable"]
75    #[inline(always)]
76    #[must_use]
77    pub fn plle(&mut self) -> PLLE_W<1> {
78        PLLE_W::new(self)
79    }
80    #[doc = "Bit 2 - PCK Enable"]
81    #[inline(always)]
82    #[must_use]
83    pub fn pcke(&mut self) -> PCKE_W<2> {
84        PCKE_W::new(self)
85    }
86    #[doc = "Bit 7 - Low speed mode"]
87    #[inline(always)]
88    #[must_use]
89    pub fn lsm(&mut self) -> LSM_W<7> {
90        LSM_W::new(self)
91    }
92    #[doc = "Writes raw bits to the register."]
93    #[inline(always)]
94    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
95        self.0.bits(bits);
96        self
97    }
98}
99#[doc = "PLL Control and status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pllcsr](index.html) module"]
100pub struct PLLCSR_SPEC;
101impl crate::RegisterSpec for PLLCSR_SPEC {
102    type Ux = u8;
103}
104#[doc = "`read()` method returns [pllcsr::R](R) reader structure"]
105impl crate::Readable for PLLCSR_SPEC {
106    type Reader = R;
107}
108#[doc = "`write(|w| ..)` method takes [pllcsr::W](W) writer structure"]
109impl crate::Writable for PLLCSR_SPEC {
110    type Writer = W;
111    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
112    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
113}
114#[doc = "`reset()` method sets PLLCSR to value 0"]
115impl crate::Resettable for PLLCSR_SPEC {
116    const RESET_VALUE: Self::Ux = 0;
117}
avr_device/devices/attiny85/cpu/pllcsr.rs

avr_device/devices/attiny85/cpu/
pllcsr.rs
