avr_device/devices/attiny85/fuse/
low.rs

1#[doc = "Register `LOW` reader"]
2pub struct R(crate::R<LOW_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LOW_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LOW_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LOW_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LOW` writer"]
17pub struct W(crate::W<LOW_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LOW_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LOW_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LOW_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SUT_CKSEL` reader - Select Clock source"]
38pub type SUT_CKSEL_R = crate::FieldReader<u8, SUT_CKSEL_A>;
39#[doc = "Select Clock source\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SUT_CKSEL_A {
43    #[doc = "0: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
44    EXTCLK_6CK_14CK_0MS = 0,
45    #[doc = "1: PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
46    PLLCLK_1KCK_14CK_4MS = 1,
47    #[doc = "2: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
48    INTRCOSC_8MHZ_6CK_14CK_0MS = 2,
49    #[doc = "3: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
50    INTRCOSC_6MHZ4_6CK_14CK_64MS = 3,
51    #[doc = "4: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
52    WDOSC_128KHZ_6CK_14CK_0MS = 4,
53    #[doc = "6: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"]
54    EXTLOFXTAL_1KCK_14CK_0MS = 6,
55    #[doc = "8: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
56    EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 8,
57    #[doc = "9: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
58    EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 9,
59    #[doc = "10: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
60    EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 10,
61    #[doc = "11: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
62    EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 11,
63    #[doc = "12: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
64    EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 12,
65    #[doc = "13: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
66    EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 13,
67    #[doc = "14: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
68    EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 14,
69    #[doc = "15: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
70    EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 15,
71    #[doc = "16: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"]
72    EXTCLK_6CK_14CK_4MS1 = 16,
73    #[doc = "17: PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms"]
74    PLLCLK_16KCK_14CK_4MS = 17,
75    #[doc = "18: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
76    INTRCOSC_8MHZ_6CK_14CK_4MS = 18,
77    #[doc = "20: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
78    WDOSC_128KHZ_6CK_14CK_4MS = 20,
79    #[doc = "22: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
80    EXTLOFXTAL_1KCK_14CK_4MS = 22,
81    #[doc = "24: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
82    EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 24,
83    #[doc = "25: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
84    EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 25,
85    #[doc = "26: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
86    EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 26,
87    #[doc = "27: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
88    EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 27,
89    #[doc = "28: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
90    EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 28,
91    #[doc = "29: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
92    EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 29,
93    #[doc = "30: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
94    EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 30,
95    #[doc = "31: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
96    EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 31,
97    #[doc = "32: Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms"]
98    EXTCLK_6CK_14CK_65MS = 32,
99    #[doc = "33: PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms"]
100    PLLCLK_1KCK_14CK_64MS = 33,
101    #[doc = "34: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
102    INTRCOSC_8MHZ_6CK_14CK_64MS = 34,
103    #[doc = "35: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
104    INTRCOSC_6MHZ4_6CK_14CK_4MS = 35,
105    #[doc = "36: WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
106    WDOSC_128KHZ_6CK_14CK_64MS = 36,
107    #[doc = "38: Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms"]
108    EXTLOFXTAL_32KCK_14CK_64MS = 38,
109    #[doc = "40: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
110    EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 40,
111    #[doc = "41: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
112    EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 41,
113    #[doc = "42: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
114    EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 42,
115    #[doc = "43: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
116    EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 43,
117    #[doc = "44: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
118    EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 44,
119    #[doc = "45: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
120    EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 45,
121    #[doc = "46: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
122    EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 46,
123    #[doc = "47: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
124    EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 47,
125    #[doc = "49: PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms"]
126    PLLCLK_16KCK_14CK_64MS = 49,
127    #[doc = "51: ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms"]
128    INTRCOSC_6MHZ4_1CK_14CK_0MS = 51,
129    #[doc = "56: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
130    EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 56,
131    #[doc = "57: Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
132    EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 57,
133    #[doc = "58: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
134    EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 58,
135    #[doc = "59: Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
136    EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 59,
137    #[doc = "60: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
138    EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 60,
139    #[doc = "61: Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
140    EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 61,
141    #[doc = "62: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
142    EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 62,
143    #[doc = "63: Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
144    EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 63,
145}
146impl From<SUT_CKSEL_A> for u8 {
147    #[inline(always)]
148    fn from(variant: SUT_CKSEL_A) -> Self {
149        variant as _
150    }
151}
152impl SUT_CKSEL_R {
153    #[doc = "Get enumerated values variant"]
154    #[inline(always)]
155    pub fn variant(&self) -> Option<SUT_CKSEL_A> {
156        match self.bits {
157            0 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS),
158            1 => Some(SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS),
159            2 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS),
160            3 => Some(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS),
161            4 => Some(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS),
162            6 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS),
163            8 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1),
164            9 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS),
165            10 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1),
166            11 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS),
167            12 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1),
168            13 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS),
169            14 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1),
170            15 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS),
171            16 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1),
172            17 => Some(SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS),
173            18 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS),
174            20 => Some(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS),
175            22 => Some(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS),
176            24 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS),
177            25 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS),
178            26 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS),
179            27 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS),
180            28 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS),
181            29 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS),
182            30 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS),
183            31 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS),
184            32 => Some(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS),
185            33 => Some(SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS),
186            34 => Some(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS),
187            35 => Some(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS),
188            36 => Some(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS),
189            38 => Some(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS),
190            40 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS),
191            41 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1),
192            42 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS),
193            43 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1),
194            44 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS),
195            45 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1),
196            46 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS),
197            47 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1),
198            49 => Some(SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS),
199            51 => Some(SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS),
200            56 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1),
201            57 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS),
202            58 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1),
203            59 => Some(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS),
204            60 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1),
205            61 => Some(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS),
206            62 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1),
207            63 => Some(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS),
208            _ => None,
209        }
210    }
211    #[doc = "Checks if the value of the field is `EXTCLK_6CK_14CK_0MS`"]
212    #[inline(always)]
213    pub fn is_extclk_6ck_14ck_0ms(&self) -> bool {
214        *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS
215    }
216    #[doc = "Checks if the value of the field is `PLLCLK_1KCK_14CK_4MS`"]
217    #[inline(always)]
218    pub fn is_pllclk_1kck_14ck_4ms(&self) -> bool {
219        *self == SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS
220    }
221    #[doc = "Checks if the value of the field is `INTRCOSC_8MHZ_6CK_14CK_0MS`"]
222    #[inline(always)]
223    pub fn is_intrcosc_8mhz_6ck_14ck_0ms(&self) -> bool {
224        *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS
225    }
226    #[doc = "Checks if the value of the field is `INTRCOSC_6MHZ4_6CK_14CK_64MS`"]
227    #[inline(always)]
228    pub fn is_intrcosc_6mhz4_6ck_14ck_64ms(&self) -> bool {
229        *self == SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS
230    }
231    #[doc = "Checks if the value of the field is `WDOSC_128KHZ_6CK_14CK_0MS`"]
232    #[inline(always)]
233    pub fn is_wdosc_128khz_6ck_14ck_0ms(&self) -> bool {
234        *self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS
235    }
236    #[doc = "Checks if the value of the field is `EXTLOFXTAL_1KCK_14CK_0MS`"]
237    #[inline(always)]
238    pub fn is_extlofxtal_1kck_14ck_0ms(&self) -> bool {
239        *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS
240    }
241    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1`"]
242    #[inline(always)]
243    pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(&self) -> bool {
244        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1
245    }
246    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS`"]
247    #[inline(always)]
248    pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_65ms(&self) -> bool {
249        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS
250    }
251    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1`"]
252    #[inline(always)]
253    pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_4ms1(&self) -> bool {
254        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1
255    }
256    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS`"]
257    #[inline(always)]
258    pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_65ms(&self) -> bool {
259        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS
260    }
261    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1`"]
262    #[inline(always)]
263    pub fn is_extxosc_3mhz_8mhz_258ck_14ck_4ms1(&self) -> bool {
264        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1
265    }
266    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS`"]
267    #[inline(always)]
268    pub fn is_extxosc_3mhz_8mhz_1kck_14ck_65ms(&self) -> bool {
269        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS
270    }
271    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_258CK_14CK_4MS1`"]
272    #[inline(always)]
273    pub fn is_extxosc_8mhz_xx_258ck_14ck_4ms1(&self) -> bool {
274        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1
275    }
276    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_1KCK_14CK_65MS`"]
277    #[inline(always)]
278    pub fn is_extxosc_8mhz_xx_1kck_14ck_65ms(&self) -> bool {
279        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS
280    }
281    #[doc = "Checks if the value of the field is `EXTCLK_6CK_14CK_4MS1`"]
282    #[inline(always)]
283    pub fn is_extclk_6ck_14ck_4ms1(&self) -> bool {
284        *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1
285    }
286    #[doc = "Checks if the value of the field is `PLLCLK_16KCK_14CK_4MS`"]
287    #[inline(always)]
288    pub fn is_pllclk_16kck_14ck_4ms(&self) -> bool {
289        *self == SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS
290    }
291    #[doc = "Checks if the value of the field is `INTRCOSC_8MHZ_6CK_14CK_4MS`"]
292    #[inline(always)]
293    pub fn is_intrcosc_8mhz_6ck_14ck_4ms(&self) -> bool {
294        *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS
295    }
296    #[doc = "Checks if the value of the field is `WDOSC_128KHZ_6CK_14CK_4MS`"]
297    #[inline(always)]
298    pub fn is_wdosc_128khz_6ck_14ck_4ms(&self) -> bool {
299        *self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS
300    }
301    #[doc = "Checks if the value of the field is `EXTLOFXTAL_1KCK_14CK_4MS`"]
302    #[inline(always)]
303    pub fn is_extlofxtal_1kck_14ck_4ms(&self) -> bool {
304        *self == SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS
305    }
306    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS`"]
307    #[inline(always)]
308    pub fn is_extxosc_0mhz4_0mhz9_258ck_14ck_65ms(&self) -> bool {
309        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS
310    }
311    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS`"]
312    #[inline(always)]
313    pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_0ms(&self) -> bool {
314        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS
315    }
316    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS`"]
317    #[inline(always)]
318    pub fn is_extxosc_0mhz9_3mhz_258ck_14ck_65ms(&self) -> bool {
319        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS
320    }
321    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS`"]
322    #[inline(always)]
323    pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_0ms(&self) -> bool {
324        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS
325    }
326    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS`"]
327    #[inline(always)]
328    pub fn is_extxosc_3mhz_8mhz_258ck_14ck_65ms(&self) -> bool {
329        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS
330    }
331    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS`"]
332    #[inline(always)]
333    pub fn is_extxosc_3mhz_8mhz_16kck_14ck_0ms(&self) -> bool {
334        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS
335    }
336    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_258CK_14CK_65MS`"]
337    #[inline(always)]
338    pub fn is_extxosc_8mhz_xx_258ck_14ck_65ms(&self) -> bool {
339        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS
340    }
341    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_16KCK_14CK_0MS`"]
342    #[inline(always)]
343    pub fn is_extxosc_8mhz_xx_16kck_14ck_0ms(&self) -> bool {
344        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS
345    }
346    #[doc = "Checks if the value of the field is `EXTCLK_6CK_14CK_65MS`"]
347    #[inline(always)]
348    pub fn is_extclk_6ck_14ck_65ms(&self) -> bool {
349        *self == SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS
350    }
351    #[doc = "Checks if the value of the field is `PLLCLK_1KCK_14CK_64MS`"]
352    #[inline(always)]
353    pub fn is_pllclk_1kck_14ck_64ms(&self) -> bool {
354        *self == SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS
355    }
356    #[doc = "Checks if the value of the field is `INTRCOSC_8MHZ_6CK_14CK_64MS`"]
357    #[inline(always)]
358    pub fn is_intrcosc_8mhz_6ck_14ck_64ms(&self) -> bool {
359        *self == SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS
360    }
361    #[doc = "Checks if the value of the field is `INTRCOSC_6MHZ4_6CK_14CK_4MS`"]
362    #[inline(always)]
363    pub fn is_intrcosc_6mhz4_6ck_14ck_4ms(&self) -> bool {
364        *self == SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS
365    }
366    #[doc = "Checks if the value of the field is `WDOSC_128KHZ_6CK_14CK_64MS`"]
367    #[inline(always)]
368    pub fn is_wdosc_128khz_6ck_14ck_64ms(&self) -> bool {
369        *self == SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS
370    }
371    #[doc = "Checks if the value of the field is `EXTLOFXTAL_32KCK_14CK_64MS`"]
372    #[inline(always)]
373    pub fn is_extlofxtal_32kck_14ck_64ms(&self) -> bool {
374        *self == SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS
375    }
376    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS`"]
377    #[inline(always)]
378    pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_0ms(&self) -> bool {
379        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS
380    }
381    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1`"]
382    #[inline(always)]
383    pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(&self) -> bool {
384        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1
385    }
386    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS`"]
387    #[inline(always)]
388    pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_0ms(&self) -> bool {
389        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS
390    }
391    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1`"]
392    #[inline(always)]
393    pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_4ms1(&self) -> bool {
394        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1
395    }
396    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS`"]
397    #[inline(always)]
398    pub fn is_extxosc_3mhz_8mhz_1kck_14ck_0ms(&self) -> bool {
399        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS
400    }
401    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1`"]
402    #[inline(always)]
403    pub fn is_extxosc_3mhz_8mhz_16kck_14ck_4ms1(&self) -> bool {
404        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1
405    }
406    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_1KCK_14CK_0MS`"]
407    #[inline(always)]
408    pub fn is_extxosc_8mhz_xx_1kck_14ck_0ms(&self) -> bool {
409        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS
410    }
411    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1`"]
412    #[inline(always)]
413    pub fn is_extxosc_8mhz_xx_16kck_14ck_4ms1(&self) -> bool {
414        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1
415    }
416    #[doc = "Checks if the value of the field is `PLLCLK_16KCK_14CK_64MS`"]
417    #[inline(always)]
418    pub fn is_pllclk_16kck_14ck_64ms(&self) -> bool {
419        *self == SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS
420    }
421    #[doc = "Checks if the value of the field is `INTRCOSC_6MHZ4_1CK_14CK_0MS`"]
422    #[inline(always)]
423    pub fn is_intrcosc_6mhz4_1ck_14ck_0ms(&self) -> bool {
424        *self == SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS
425    }
426    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1`"]
427    #[inline(always)]
428    pub fn is_extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(&self) -> bool {
429        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1
430    }
431    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS`"]
432    #[inline(always)]
433    pub fn is_extxosc_0mhz4_0mhz9_16kck_14ck_65ms(&self) -> bool {
434        *self == SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS
435    }
436    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1`"]
437    #[inline(always)]
438    pub fn is_extxosc_0mhz9_3mhz_1kck_14ck_4ms1(&self) -> bool {
439        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1
440    }
441    #[doc = "Checks if the value of the field is `EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS`"]
442    #[inline(always)]
443    pub fn is_extxosc_0mhz9_3mhz_16kck_14ck_65ms(&self) -> bool {
444        *self == SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS
445    }
446    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1`"]
447    #[inline(always)]
448    pub fn is_extxosc_3mhz_8mhz_1kck_14ck_4ms1(&self) -> bool {
449        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1
450    }
451    #[doc = "Checks if the value of the field is `EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS`"]
452    #[inline(always)]
453    pub fn is_extxosc_3mhz_8mhz_16kck_14ck_65ms(&self) -> bool {
454        *self == SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS
455    }
456    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1`"]
457    #[inline(always)]
458    pub fn is_extxosc_8mhz_xx_1kck_14ck_4ms1(&self) -> bool {
459        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1
460    }
461    #[doc = "Checks if the value of the field is `EXTXOSC_8MHZ_XX_16KCK_14CK_65MS`"]
462    #[inline(always)]
463    pub fn is_extxosc_8mhz_xx_16kck_14ck_65ms(&self) -> bool {
464        *self == SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS
465    }
466}
467#[doc = "Field `SUT_CKSEL` writer - Select Clock source"]
468pub type SUT_CKSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u8, LOW_SPEC, u8, SUT_CKSEL_A, 6, O>;
469impl<'a, const O: u8> SUT_CKSEL_W<'a, O> {
470    #[doc = "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
471    #[inline(always)]
472    pub fn extclk_6ck_14ck_0ms(self) -> &'a mut W {
473        self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_0MS)
474    }
475    #[doc = "PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
476    #[inline(always)]
477    pub fn pllclk_1kck_14ck_4ms(self) -> &'a mut W {
478        self.variant(SUT_CKSEL_A::PLLCLK_1KCK_14CK_4MS)
479    }
480    #[doc = "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
481    #[inline(always)]
482    pub fn intrcosc_8mhz_6ck_14ck_0ms(self) -> &'a mut W {
483        self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_0MS)
484    }
485    #[doc = "ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
486    #[inline(always)]
487    pub fn intrcosc_6mhz4_6ck_14ck_64ms(self) -> &'a mut W {
488        self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_64MS)
489    }
490    #[doc = "WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms"]
491    #[inline(always)]
492    pub fn wdosc_128khz_6ck_14ck_0ms(self) -> &'a mut W {
493        self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_0MS)
494    }
495    #[doc = "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms"]
496    #[inline(always)]
497    pub fn extlofxtal_1kck_14ck_0ms(self) -> &'a mut W {
498        self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_0MS)
499    }
500    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
501    #[inline(always)]
502    pub fn extxosc_0mhz4_0mhz9_258ck_14ck_4ms1(self) -> &'a mut W {
503        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1)
504    }
505    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
506    #[inline(always)]
507    pub fn extxosc_0mhz4_0mhz9_1kck_14ck_65ms(self) -> &'a mut W {
508        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS)
509    }
510    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
511    #[inline(always)]
512    pub fn extxosc_0mhz9_3mhz_258ck_14ck_4ms1(self) -> &'a mut W {
513        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1)
514    }
515    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
516    #[inline(always)]
517    pub fn extxosc_0mhz9_3mhz_1kck_14ck_65ms(self) -> &'a mut W {
518        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS)
519    }
520    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
521    #[inline(always)]
522    pub fn extxosc_3mhz_8mhz_258ck_14ck_4ms1(self) -> &'a mut W {
523        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1)
524    }
525    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
526    #[inline(always)]
527    pub fn extxosc_3mhz_8mhz_1kck_14ck_65ms(self) -> &'a mut W {
528        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS)
529    }
530    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"]
531    #[inline(always)]
532    pub fn extxosc_8mhz_xx_258ck_14ck_4ms1(self) -> &'a mut W {
533        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_4MS1)
534    }
535    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms"]
536    #[inline(always)]
537    pub fn extxosc_8mhz_xx_1kck_14ck_65ms(self) -> &'a mut W {
538        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_65MS)
539    }
540    #[doc = "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"]
541    #[inline(always)]
542    pub fn extclk_6ck_14ck_4ms1(self) -> &'a mut W {
543        self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_4MS1)
544    }
545    #[doc = "PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms"]
546    #[inline(always)]
547    pub fn pllclk_16kck_14ck_4ms(self) -> &'a mut W {
548        self.variant(SUT_CKSEL_A::PLLCLK_16KCK_14CK_4MS)
549    }
550    #[doc = "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
551    #[inline(always)]
552    pub fn intrcosc_8mhz_6ck_14ck_4ms(self) -> &'a mut W {
553        self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_4MS)
554    }
555    #[doc = "WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
556    #[inline(always)]
557    pub fn wdosc_128khz_6ck_14ck_4ms(self) -> &'a mut W {
558        self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_4MS)
559    }
560    #[doc = "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms"]
561    #[inline(always)]
562    pub fn extlofxtal_1kck_14ck_4ms(self) -> &'a mut W {
563        self.variant(SUT_CKSEL_A::EXTLOFXTAL_1KCK_14CK_4MS)
564    }
565    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
566    #[inline(always)]
567    pub fn extxosc_0mhz4_0mhz9_258ck_14ck_65ms(self) -> &'a mut W {
568        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS)
569    }
570    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
571    #[inline(always)]
572    pub fn extxosc_0mhz4_0mhz9_16kck_14ck_0ms(self) -> &'a mut W {
573        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS)
574    }
575    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
576    #[inline(always)]
577    pub fn extxosc_0mhz9_3mhz_258ck_14ck_65ms(self) -> &'a mut W {
578        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS)
579    }
580    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
581    #[inline(always)]
582    pub fn extxosc_0mhz9_3mhz_16kck_14ck_0ms(self) -> &'a mut W {
583        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS)
584    }
585    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
586    #[inline(always)]
587    pub fn extxosc_3mhz_8mhz_258ck_14ck_65ms(self) -> &'a mut W {
588        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS)
589    }
590    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
591    #[inline(always)]
592    pub fn extxosc_3mhz_8mhz_16kck_14ck_0ms(self) -> &'a mut W {
593        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS)
594    }
595    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms"]
596    #[inline(always)]
597    pub fn extxosc_8mhz_xx_258ck_14ck_65ms(self) -> &'a mut W {
598        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_258CK_14CK_65MS)
599    }
600    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms"]
601    #[inline(always)]
602    pub fn extxosc_8mhz_xx_16kck_14ck_0ms(self) -> &'a mut W {
603        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_0MS)
604    }
605    #[doc = "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms"]
606    #[inline(always)]
607    pub fn extclk_6ck_14ck_65ms(self) -> &'a mut W {
608        self.variant(SUT_CKSEL_A::EXTCLK_6CK_14CK_65MS)
609    }
610    #[doc = "PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms"]
611    #[inline(always)]
612    pub fn pllclk_1kck_14ck_64ms(self) -> &'a mut W {
613        self.variant(SUT_CKSEL_A::PLLCLK_1KCK_14CK_64MS)
614    }
615    #[doc = "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
616    #[inline(always)]
617    pub fn intrcosc_8mhz_6ck_14ck_64ms(self) -> &'a mut W {
618        self.variant(SUT_CKSEL_A::INTRCOSC_8MHZ_6CK_14CK_64MS)
619    }
620    #[doc = "ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms"]
621    #[inline(always)]
622    pub fn intrcosc_6mhz4_6ck_14ck_4ms(self) -> &'a mut W {
623        self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_6CK_14CK_4MS)
624    }
625    #[doc = "WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms"]
626    #[inline(always)]
627    pub fn wdosc_128khz_6ck_14ck_64ms(self) -> &'a mut W {
628        self.variant(SUT_CKSEL_A::WDOSC_128KHZ_6CK_14CK_64MS)
629    }
630    #[doc = "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms"]
631    #[inline(always)]
632    pub fn extlofxtal_32kck_14ck_64ms(self) -> &'a mut W {
633        self.variant(SUT_CKSEL_A::EXTLOFXTAL_32KCK_14CK_64MS)
634    }
635    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
636    #[inline(always)]
637    pub fn extxosc_0mhz4_0mhz9_1kck_14ck_0ms(self) -> &'a mut W {
638        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS)
639    }
640    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
641    #[inline(always)]
642    pub fn extxosc_0mhz4_0mhz9_16kck_14ck_4ms1(self) -> &'a mut W {
643        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1)
644    }
645    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
646    #[inline(always)]
647    pub fn extxosc_0mhz9_3mhz_1kck_14ck_0ms(self) -> &'a mut W {
648        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS)
649    }
650    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
651    #[inline(always)]
652    pub fn extxosc_0mhz9_3mhz_16kck_14ck_4ms1(self) -> &'a mut W {
653        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1)
654    }
655    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
656    #[inline(always)]
657    pub fn extxosc_3mhz_8mhz_1kck_14ck_0ms(self) -> &'a mut W {
658        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS)
659    }
660    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
661    #[inline(always)]
662    pub fn extxosc_3mhz_8mhz_16kck_14ck_4ms1(self) -> &'a mut W {
663        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1)
664    }
665    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms"]
666    #[inline(always)]
667    pub fn extxosc_8mhz_xx_1kck_14ck_0ms(self) -> &'a mut W {
668        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_0MS)
669    }
670    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms"]
671    #[inline(always)]
672    pub fn extxosc_8mhz_xx_16kck_14ck_4ms1(self) -> &'a mut W {
673        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1)
674    }
675    #[doc = "PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms"]
676    #[inline(always)]
677    pub fn pllclk_16kck_14ck_64ms(self) -> &'a mut W {
678        self.variant(SUT_CKSEL_A::PLLCLK_16KCK_14CK_64MS)
679    }
680    #[doc = "ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms"]
681    #[inline(always)]
682    pub fn intrcosc_6mhz4_1ck_14ck_0ms(self) -> &'a mut W {
683        self.variant(SUT_CKSEL_A::INTRCOSC_6MHZ4_1CK_14CK_0MS)
684    }
685    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
686    #[inline(always)]
687    pub fn extxosc_0mhz4_0mhz9_1kck_14ck_4ms1(self) -> &'a mut W {
688        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1)
689    }
690    #[doc = "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
691    #[inline(always)]
692    pub fn extxosc_0mhz4_0mhz9_16kck_14ck_65ms(self) -> &'a mut W {
693        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS)
694    }
695    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
696    #[inline(always)]
697    pub fn extxosc_0mhz9_3mhz_1kck_14ck_4ms1(self) -> &'a mut W {
698        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1)
699    }
700    #[doc = "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
701    #[inline(always)]
702    pub fn extxosc_0mhz9_3mhz_16kck_14ck_65ms(self) -> &'a mut W {
703        self.variant(SUT_CKSEL_A::EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS)
704    }
705    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
706    #[inline(always)]
707    pub fn extxosc_3mhz_8mhz_1kck_14ck_4ms1(self) -> &'a mut W {
708        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1)
709    }
710    #[doc = "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
711    #[inline(always)]
712    pub fn extxosc_3mhz_8mhz_16kck_14ck_65ms(self) -> &'a mut W {
713        self.variant(SUT_CKSEL_A::EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS)
714    }
715    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms"]
716    #[inline(always)]
717    pub fn extxosc_8mhz_xx_1kck_14ck_4ms1(self) -> &'a mut W {
718        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1)
719    }
720    #[doc = "Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms"]
721    #[inline(always)]
722    pub fn extxosc_8mhz_xx_16kck_14ck_65ms(self) -> &'a mut W {
723        self.variant(SUT_CKSEL_A::EXTXOSC_8MHZ_XX_16KCK_14CK_65MS)
724    }
725}
726#[doc = "Field `CKOUT` reader - Clock output on PORTB4"]
727pub type CKOUT_R = crate::BitReader<bool>;
728#[doc = "Field `CKOUT` writer - Clock output on PORTB4"]
729pub type CKOUT_W<'a, const O: u8> = crate::BitWriter<'a, u8, LOW_SPEC, bool, O>;
730#[doc = "Field `CKDIV8` reader - Divide clock by 8 internally"]
731pub type CKDIV8_R = crate::BitReader<bool>;
732#[doc = "Field `CKDIV8` writer - Divide clock by 8 internally"]
733pub type CKDIV8_W<'a, const O: u8> = crate::BitWriter<'a, u8, LOW_SPEC, bool, O>;
734impl R {
735    #[doc = "Bits 0:5 - Select Clock source"]
736    #[inline(always)]
737    pub fn sut_cksel(&self) -> SUT_CKSEL_R {
738        SUT_CKSEL_R::new(self.bits & 0x3f)
739    }
740    #[doc = "Bit 6 - Clock output on PORTB4"]
741    #[inline(always)]
742    pub fn ckout(&self) -> CKOUT_R {
743        CKOUT_R::new(((self.bits >> 6) & 1) != 0)
744    }
745    #[doc = "Bit 7 - Divide clock by 8 internally"]
746    #[inline(always)]
747    pub fn ckdiv8(&self) -> CKDIV8_R {
748        CKDIV8_R::new(((self.bits >> 7) & 1) != 0)
749    }
750}
751impl W {
752    #[doc = "Bits 0:5 - Select Clock source"]
753    #[inline(always)]
754    #[must_use]
755    pub fn sut_cksel(&mut self) -> SUT_CKSEL_W<0> {
756        SUT_CKSEL_W::new(self)
757    }
758    #[doc = "Bit 6 - Clock output on PORTB4"]
759    #[inline(always)]
760    #[must_use]
761    pub fn ckout(&mut self) -> CKOUT_W<6> {
762        CKOUT_W::new(self)
763    }
764    #[doc = "Bit 7 - Divide clock by 8 internally"]
765    #[inline(always)]
766    #[must_use]
767    pub fn ckdiv8(&mut self) -> CKDIV8_W<7> {
768        CKDIV8_W::new(self)
769    }
770    #[doc = "Writes raw bits to the register."]
771    #[inline(always)]
772    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
773        self.0.bits(bits);
774        self
775    }
776}
777#[doc = "No Description.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [low](index.html) module"]
778pub struct LOW_SPEC;
779impl crate::RegisterSpec for LOW_SPEC {
780    type Ux = u8;
781}
782#[doc = "`read()` method returns [low::R](R) reader structure"]
783impl crate::Readable for LOW_SPEC {
784    type Reader = R;
785}
786#[doc = "`write(|w| ..)` method takes [low::W](W) writer structure"]
787impl crate::Writable for LOW_SPEC {
788    type Writer = W;
789    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
790    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
791}
792#[doc = "`reset()` method sets LOW to value 0"]
793impl crate::Resettable for LOW_SPEC {
794    const RESET_VALUE: Self::Ux = 0;
795}
avr_device/devices/attiny85/fuse/low.rs

avr_device/devices/attiny85/fuse/
low.rs
