avr_device/devices/attiny85/usi/
usicr.rs

1#[doc = "Register `USICR` reader"]
2pub struct R(crate::R<USICR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<USICR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<USICR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<USICR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `USICR` writer"]
17pub struct W(crate::W<USICR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<USICR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<USICR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<USICR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `USITC` writer - Toggle Clock Port Pin"]
38pub type USITC_W<'a, const O: u8> = crate::BitWriter<'a, u8, USICR_SPEC, bool, O>;
39#[doc = "Field `USICLK` writer - Clock Strobe"]
40pub type USICLK_W<'a, const O: u8> = crate::BitWriter<'a, u8, USICR_SPEC, bool, O>;
41#[doc = "Field `USICS` reader - USI Clock Source Select Bits"]
42pub type USICS_R = crate::FieldReader<u8, USICS_A>;
43#[doc = "USI Clock Source Select Bits\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum USICS_A {
47    #[doc = "0: No Clock/Software clock strobe"]
48    NO_CLOCK = 0,
49    #[doc = "1: Timer/Counter0 Compare Match"]
50    TC0 = 1,
51    #[doc = "2: External, positive edge"]
52    EXT_POS = 2,
53    #[doc = "3: External, negative edge"]
54    EXT_NEG = 3,
55}
56impl From<USICS_A> for u8 {
57    #[inline(always)]
58    fn from(variant: USICS_A) -> Self {
59        variant as _
60    }
61}
62impl USICS_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> USICS_A {
66        match self.bits {
67            0 => USICS_A::NO_CLOCK,
68            1 => USICS_A::TC0,
69            2 => USICS_A::EXT_POS,
70            3 => USICS_A::EXT_NEG,
71            _ => unreachable!(),
72        }
73    }
74    #[doc = "Checks if the value of the field is `NO_CLOCK`"]
75    #[inline(always)]
76    pub fn is_no_clock(&self) -> bool {
77        *self == USICS_A::NO_CLOCK
78    }
79    #[doc = "Checks if the value of the field is `TC0`"]
80    #[inline(always)]
81    pub fn is_tc0(&self) -> bool {
82        *self == USICS_A::TC0
83    }
84    #[doc = "Checks if the value of the field is `EXT_POS`"]
85    #[inline(always)]
86    pub fn is_ext_pos(&self) -> bool {
87        *self == USICS_A::EXT_POS
88    }
89    #[doc = "Checks if the value of the field is `EXT_NEG`"]
90    #[inline(always)]
91    pub fn is_ext_neg(&self) -> bool {
92        *self == USICS_A::EXT_NEG
93    }
94}
95#[doc = "Field `USICS` writer - USI Clock Source Select Bits"]
96pub type USICS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, USICR_SPEC, u8, USICS_A, 2, O>;
97impl<'a, const O: u8> USICS_W<'a, O> {
98    #[doc = "No Clock/Software clock strobe"]
99    #[inline(always)]
100    pub fn no_clock(self) -> &'a mut W {
101        self.variant(USICS_A::NO_CLOCK)
102    }
103    #[doc = "Timer/Counter0 Compare Match"]
104    #[inline(always)]
105    pub fn tc0(self) -> &'a mut W {
106        self.variant(USICS_A::TC0)
107    }
108    #[doc = "External, positive edge"]
109    #[inline(always)]
110    pub fn ext_pos(self) -> &'a mut W {
111        self.variant(USICS_A::EXT_POS)
112    }
113    #[doc = "External, negative edge"]
114    #[inline(always)]
115    pub fn ext_neg(self) -> &'a mut W {
116        self.variant(USICS_A::EXT_NEG)
117    }
118}
119#[doc = "Field `USIWM` reader - USI Wire Mode Bits"]
120pub type USIWM_R = crate::FieldReader<u8, USIWM_A>;
121#[doc = "USI Wire Mode Bits\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123#[repr(u8)]
124pub enum USIWM_A {
125    #[doc = "0: All detectors disabled. Port pins operates as normal."]
126    DISABLED = 0,
127    #[doc = "1: Three-wire mode. Uses DO, DI, and USCK pins."]
128    THREE_WIRE = 1,
129    #[doc = "2: Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."]
130    TWO_WIRE_SLAVE = 2,
131    #[doc = "3: Two-wire mode (Master). Uses SDA and SCL pins."]
132    TWO_WIRE_MASTER = 3,
133}
134impl From<USIWM_A> for u8 {
135    #[inline(always)]
136    fn from(variant: USIWM_A) -> Self {
137        variant as _
138    }
139}
140impl USIWM_R {
141    #[doc = "Get enumerated values variant"]
142    #[inline(always)]
143    pub fn variant(&self) -> USIWM_A {
144        match self.bits {
145            0 => USIWM_A::DISABLED,
146            1 => USIWM_A::THREE_WIRE,
147            2 => USIWM_A::TWO_WIRE_SLAVE,
148            3 => USIWM_A::TWO_WIRE_MASTER,
149            _ => unreachable!(),
150        }
151    }
152    #[doc = "Checks if the value of the field is `DISABLED`"]
153    #[inline(always)]
154    pub fn is_disabled(&self) -> bool {
155        *self == USIWM_A::DISABLED
156    }
157    #[doc = "Checks if the value of the field is `THREE_WIRE`"]
158    #[inline(always)]
159    pub fn is_three_wire(&self) -> bool {
160        *self == USIWM_A::THREE_WIRE
161    }
162    #[doc = "Checks if the value of the field is `TWO_WIRE_SLAVE`"]
163    #[inline(always)]
164    pub fn is_two_wire_slave(&self) -> bool {
165        *self == USIWM_A::TWO_WIRE_SLAVE
166    }
167    #[doc = "Checks if the value of the field is `TWO_WIRE_MASTER`"]
168    #[inline(always)]
169    pub fn is_two_wire_master(&self) -> bool {
170        *self == USIWM_A::TWO_WIRE_MASTER
171    }
172}
173#[doc = "Field `USIWM` writer - USI Wire Mode Bits"]
174pub type USIWM_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, USICR_SPEC, u8, USIWM_A, 2, O>;
175impl<'a, const O: u8> USIWM_W<'a, O> {
176    #[doc = "All detectors disabled. Port pins operates as normal."]
177    #[inline(always)]
178    pub fn disabled(self) -> &'a mut W {
179        self.variant(USIWM_A::DISABLED)
180    }
181    #[doc = "Three-wire mode. Uses DO, DI, and USCK pins."]
182    #[inline(always)]
183    pub fn three_wire(self) -> &'a mut W {
184        self.variant(USIWM_A::THREE_WIRE)
185    }
186    #[doc = "Two-wire mode (Slave). Uses SDA (DI) and SCL (USCK) pins."]
187    #[inline(always)]
188    pub fn two_wire_slave(self) -> &'a mut W {
189        self.variant(USIWM_A::TWO_WIRE_SLAVE)
190    }
191    #[doc = "Two-wire mode (Master). Uses SDA and SCL pins."]
192    #[inline(always)]
193    pub fn two_wire_master(self) -> &'a mut W {
194        self.variant(USIWM_A::TWO_WIRE_MASTER)
195    }
196}
197#[doc = "Field `USIOIE` reader - Counter Overflow Interrupt Enable"]
198pub type USIOIE_R = crate::BitReader<bool>;
199#[doc = "Field `USIOIE` writer - Counter Overflow Interrupt Enable"]
200pub type USIOIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, USICR_SPEC, bool, O>;
201#[doc = "Field `USISIE` reader - Start Condition Interrupt Enable"]
202pub type USISIE_R = crate::BitReader<bool>;
203#[doc = "Field `USISIE` writer - Start Condition Interrupt Enable"]
204pub type USISIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, USICR_SPEC, bool, O>;
205impl R {
206    #[doc = "Bits 2:3 - USI Clock Source Select Bits"]
207    #[inline(always)]
208    pub fn usics(&self) -> USICS_R {
209        USICS_R::new((self.bits >> 2) & 3)
210    }
211    #[doc = "Bits 4:5 - USI Wire Mode Bits"]
212    #[inline(always)]
213    pub fn usiwm(&self) -> USIWM_R {
214        USIWM_R::new((self.bits >> 4) & 3)
215    }
216    #[doc = "Bit 6 - Counter Overflow Interrupt Enable"]
217    #[inline(always)]
218    pub fn usioie(&self) -> USIOIE_R {
219        USIOIE_R::new(((self.bits >> 6) & 1) != 0)
220    }
221    #[doc = "Bit 7 - Start Condition Interrupt Enable"]
222    #[inline(always)]
223    pub fn usisie(&self) -> USISIE_R {
224        USISIE_R::new(((self.bits >> 7) & 1) != 0)
225    }
226}
227impl W {
228    #[doc = "Bit 0 - Toggle Clock Port Pin"]
229    #[inline(always)]
230    #[must_use]
231    pub fn usitc(&mut self) -> USITC_W<0> {
232        USITC_W::new(self)
233    }
234    #[doc = "Bit 1 - Clock Strobe"]
235    #[inline(always)]
236    #[must_use]
237    pub fn usiclk(&mut self) -> USICLK_W<1> {
238        USICLK_W::new(self)
239    }
240    #[doc = "Bits 2:3 - USI Clock Source Select Bits"]
241    #[inline(always)]
242    #[must_use]
243    pub fn usics(&mut self) -> USICS_W<2> {
244        USICS_W::new(self)
245    }
246    #[doc = "Bits 4:5 - USI Wire Mode Bits"]
247    #[inline(always)]
248    #[must_use]
249    pub fn usiwm(&mut self) -> USIWM_W<4> {
250        USIWM_W::new(self)
251    }
252    #[doc = "Bit 6 - Counter Overflow Interrupt Enable"]
253    #[inline(always)]
254    #[must_use]
255    pub fn usioie(&mut self) -> USIOIE_W<6> {
256        USIOIE_W::new(self)
257    }
258    #[doc = "Bit 7 - Start Condition Interrupt Enable"]
259    #[inline(always)]
260    #[must_use]
261    pub fn usisie(&mut self) -> USISIE_W<7> {
262        USISIE_W::new(self)
263    }
264    #[doc = "Writes raw bits to the register."]
265    #[inline(always)]
266    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
267        self.0.bits(bits);
268        self
269    }
270}
271#[doc = "USI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [usicr](index.html) module"]
272pub struct USICR_SPEC;
273impl crate::RegisterSpec for USICR_SPEC {
274    type Ux = u8;
275}
276#[doc = "`read()` method returns [usicr::R](R) reader structure"]
277impl crate::Readable for USICR_SPEC {
278    type Reader = R;
279}
280#[doc = "`write(|w| ..)` method takes [usicr::W](W) writer structure"]
281impl crate::Writable for USICR_SPEC {
282    type Writer = W;
283    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
284    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
285}
286#[doc = "`reset()` method sets USICR to value 0"]
287impl crate::Resettable for USICR_SPEC {
288    const RESET_VALUE: Self::Ux = 0;
289}
avr_device/devices/attiny85/usi/usicr.rs

avr_device/devices/attiny85/usi/
usicr.rs
