avr_device/devices/atmega2560/portl/
portl.rs1#[doc = "Register `PORTL` reader"]
2pub struct R(crate::R<PORTL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PORTL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PORTL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PORTL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PORTL` writer"]
17pub struct W(crate::W<PORTL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PORTL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PORTL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PORTL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `PL0` reader - Pin L0"]
38pub type PL0_R = crate::BitReader<bool>;
39#[doc = "Field `PL0` writer - Pin L0"]
40pub type PL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
41#[doc = "Field `PL1` reader - Pin L1"]
42pub type PL1_R = crate::BitReader<bool>;
43#[doc = "Field `PL1` writer - Pin L1"]
44pub type PL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
45#[doc = "Field `PL2` reader - Pin L2"]
46pub type PL2_R = crate::BitReader<bool>;
47#[doc = "Field `PL2` writer - Pin L2"]
48pub type PL2_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
49#[doc = "Field `PL3` reader - Pin L3"]
50pub type PL3_R = crate::BitReader<bool>;
51#[doc = "Field `PL3` writer - Pin L3"]
52pub type PL3_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
53#[doc = "Field `PL4` reader - Pin L4"]
54pub type PL4_R = crate::BitReader<bool>;
55#[doc = "Field `PL4` writer - Pin L4"]
56pub type PL4_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
57#[doc = "Field `PL5` reader - Pin L5"]
58pub type PL5_R = crate::BitReader<bool>;
59#[doc = "Field `PL5` writer - Pin L5"]
60pub type PL5_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
61#[doc = "Field `PL6` reader - Pin L6"]
62pub type PL6_R = crate::BitReader<bool>;
63#[doc = "Field `PL6` writer - Pin L6"]
64pub type PL6_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
65#[doc = "Field `PL7` reader - Pin L7"]
66pub type PL7_R = crate::BitReader<bool>;
67#[doc = "Field `PL7` writer - Pin L7"]
68pub type PL7_W<'a, const O: u8> = crate::BitWriter<'a, u8, PORTL_SPEC, bool, O>;
69impl R {
70 #[doc = "Bit 0 - Pin L0"]
71 #[inline(always)]
72 pub fn pl0(&self) -> PL0_R {
73 PL0_R::new((self.bits & 1) != 0)
74 }
75 #[doc = "Bit 1 - Pin L1"]
76 #[inline(always)]
77 pub fn pl1(&self) -> PL1_R {
78 PL1_R::new(((self.bits >> 1) & 1) != 0)
79 }
80 #[doc = "Bit 2 - Pin L2"]
81 #[inline(always)]
82 pub fn pl2(&self) -> PL2_R {
83 PL2_R::new(((self.bits >> 2) & 1) != 0)
84 }
85 #[doc = "Bit 3 - Pin L3"]
86 #[inline(always)]
87 pub fn pl3(&self) -> PL3_R {
88 PL3_R::new(((self.bits >> 3) & 1) != 0)
89 }
90 #[doc = "Bit 4 - Pin L4"]
91 #[inline(always)]
92 pub fn pl4(&self) -> PL4_R {
93 PL4_R::new(((self.bits >> 4) & 1) != 0)
94 }
95 #[doc = "Bit 5 - Pin L5"]
96 #[inline(always)]
97 pub fn pl5(&self) -> PL5_R {
98 PL5_R::new(((self.bits >> 5) & 1) != 0)
99 }
100 #[doc = "Bit 6 - Pin L6"]
101 #[inline(always)]
102 pub fn pl6(&self) -> PL6_R {
103 PL6_R::new(((self.bits >> 6) & 1) != 0)
104 }
105 #[doc = "Bit 7 - Pin L7"]
106 #[inline(always)]
107 pub fn pl7(&self) -> PL7_R {
108 PL7_R::new(((self.bits >> 7) & 1) != 0)
109 }
110}
111impl W {
112 #[doc = "Bit 0 - Pin L0"]
113 #[inline(always)]
114 #[must_use]
115 pub fn pl0(&mut self) -> PL0_W<0> {
116 PL0_W::new(self)
117 }
118 #[doc = "Bit 1 - Pin L1"]
119 #[inline(always)]
120 #[must_use]
121 pub fn pl1(&mut self) -> PL1_W<1> {
122 PL1_W::new(self)
123 }
124 #[doc = "Bit 2 - Pin L2"]
125 #[inline(always)]
126 #[must_use]
127 pub fn pl2(&mut self) -> PL2_W<2> {
128 PL2_W::new(self)
129 }
130 #[doc = "Bit 3 - Pin L3"]
131 #[inline(always)]
132 #[must_use]
133 pub fn pl3(&mut self) -> PL3_W<3> {
134 PL3_W::new(self)
135 }
136 #[doc = "Bit 4 - Pin L4"]
137 #[inline(always)]
138 #[must_use]
139 pub fn pl4(&mut self) -> PL4_W<4> {
140 PL4_W::new(self)
141 }
142 #[doc = "Bit 5 - Pin L5"]
143 #[inline(always)]
144 #[must_use]
145 pub fn pl5(&mut self) -> PL5_W<5> {
146 PL5_W::new(self)
147 }
148 #[doc = "Bit 6 - Pin L6"]
149 #[inline(always)]
150 #[must_use]
151 pub fn pl6(&mut self) -> PL6_W<6> {
152 PL6_W::new(self)
153 }
154 #[doc = "Bit 7 - Pin L7"]
155 #[inline(always)]
156 #[must_use]
157 pub fn pl7(&mut self) -> PL7_W<7> {
158 PL7_W::new(self)
159 }
160 #[doc = "Writes raw bits to the register."]
161 #[inline(always)]
162 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
163 self.0.bits(bits);
164 self
165 }
166}
167#[doc = "PORT L Data Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [portl](index.html) module"]
168pub struct PORTL_SPEC;
169impl crate::RegisterSpec for PORTL_SPEC {
170 type Ux = u8;
171}
172#[doc = "`read()` method returns [portl::R](R) reader structure"]
173impl crate::Readable for PORTL_SPEC {
174 type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [portl::W](W) writer structure"]
177impl crate::Writable for PORTL_SPEC {
178 type Writer = W;
179 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets PORTL to value 0"]
183impl crate::Resettable for PORTL_SPEC {
184 const RESET_VALUE: Self::Ux = 0;
185}