avr_device/devices/atmega328p/portc/
ddrc.rs1#[doc = "Register `DDRC` reader"]
2pub struct R(crate::R<DDRC_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DDRC_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DDRC_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DDRC_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `DDRC` writer"]
17pub struct W(crate::W<DDRC_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DDRC_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DDRC_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DDRC_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `PC0` reader - Pin C0"]
38pub type PC0_R = crate::BitReader<bool>;
39#[doc = "Field `PC0` writer - Pin C0"]
40pub type PC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
41#[doc = "Field `PC1` reader - Pin C1"]
42pub type PC1_R = crate::BitReader<bool>;
43#[doc = "Field `PC1` writer - Pin C1"]
44pub type PC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
45#[doc = "Field `PC2` reader - Pin C2"]
46pub type PC2_R = crate::BitReader<bool>;
47#[doc = "Field `PC2` writer - Pin C2"]
48pub type PC2_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
49#[doc = "Field `PC3` reader - Pin C3"]
50pub type PC3_R = crate::BitReader<bool>;
51#[doc = "Field `PC3` writer - Pin C3"]
52pub type PC3_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
53#[doc = "Field `PC4` reader - Pin C4"]
54pub type PC4_R = crate::BitReader<bool>;
55#[doc = "Field `PC4` writer - Pin C4"]
56pub type PC4_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
57#[doc = "Field `PC5` reader - Pin C5"]
58pub type PC5_R = crate::BitReader<bool>;
59#[doc = "Field `PC5` writer - Pin C5"]
60pub type PC5_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
61#[doc = "Field `PC6` reader - Pin C6"]
62pub type PC6_R = crate::BitReader<bool>;
63#[doc = "Field `PC6` writer - Pin C6"]
64pub type PC6_W<'a, const O: u8> = crate::BitWriter<'a, u8, DDRC_SPEC, bool, O>;
65impl R {
66 #[doc = "Bit 0 - Pin C0"]
67 #[inline(always)]
68 pub fn pc0(&self) -> PC0_R {
69 PC0_R::new((self.bits & 1) != 0)
70 }
71 #[doc = "Bit 1 - Pin C1"]
72 #[inline(always)]
73 pub fn pc1(&self) -> PC1_R {
74 PC1_R::new(((self.bits >> 1) & 1) != 0)
75 }
76 #[doc = "Bit 2 - Pin C2"]
77 #[inline(always)]
78 pub fn pc2(&self) -> PC2_R {
79 PC2_R::new(((self.bits >> 2) & 1) != 0)
80 }
81 #[doc = "Bit 3 - Pin C3"]
82 #[inline(always)]
83 pub fn pc3(&self) -> PC3_R {
84 PC3_R::new(((self.bits >> 3) & 1) != 0)
85 }
86 #[doc = "Bit 4 - Pin C4"]
87 #[inline(always)]
88 pub fn pc4(&self) -> PC4_R {
89 PC4_R::new(((self.bits >> 4) & 1) != 0)
90 }
91 #[doc = "Bit 5 - Pin C5"]
92 #[inline(always)]
93 pub fn pc5(&self) -> PC5_R {
94 PC5_R::new(((self.bits >> 5) & 1) != 0)
95 }
96 #[doc = "Bit 6 - Pin C6"]
97 #[inline(always)]
98 pub fn pc6(&self) -> PC6_R {
99 PC6_R::new(((self.bits >> 6) & 1) != 0)
100 }
101}
102impl W {
103 #[doc = "Bit 0 - Pin C0"]
104 #[inline(always)]
105 #[must_use]
106 pub fn pc0(&mut self) -> PC0_W<0> {
107 PC0_W::new(self)
108 }
109 #[doc = "Bit 1 - Pin C1"]
110 #[inline(always)]
111 #[must_use]
112 pub fn pc1(&mut self) -> PC1_W<1> {
113 PC1_W::new(self)
114 }
115 #[doc = "Bit 2 - Pin C2"]
116 #[inline(always)]
117 #[must_use]
118 pub fn pc2(&mut self) -> PC2_W<2> {
119 PC2_W::new(self)
120 }
121 #[doc = "Bit 3 - Pin C3"]
122 #[inline(always)]
123 #[must_use]
124 pub fn pc3(&mut self) -> PC3_W<3> {
125 PC3_W::new(self)
126 }
127 #[doc = "Bit 4 - Pin C4"]
128 #[inline(always)]
129 #[must_use]
130 pub fn pc4(&mut self) -> PC4_W<4> {
131 PC4_W::new(self)
132 }
133 #[doc = "Bit 5 - Pin C5"]
134 #[inline(always)]
135 #[must_use]
136 pub fn pc5(&mut self) -> PC5_W<5> {
137 PC5_W::new(self)
138 }
139 #[doc = "Bit 6 - Pin C6"]
140 #[inline(always)]
141 #[must_use]
142 pub fn pc6(&mut self) -> PC6_W<6> {
143 PC6_W::new(self)
144 }
145 #[doc = "Writes raw bits to the register."]
146 #[inline(always)]
147 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
148 self.0.bits(bits);
149 self
150 }
151}
152#[doc = "Port C Data Direction Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ddrc](index.html) module"]
153pub struct DDRC_SPEC;
154impl crate::RegisterSpec for DDRC_SPEC {
155 type Ux = u8;
156}
157#[doc = "`read()` method returns [ddrc::R](R) reader structure"]
158impl crate::Readable for DDRC_SPEC {
159 type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [ddrc::W](W) writer structure"]
162impl crate::Writable for DDRC_SPEC {
163 type Writer = W;
164 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets DDRC to value 0"]
168impl crate::Resettable for DDRC_SPEC {
169 const RESET_VALUE: Self::Ux = 0;
170}