avr_device/devices/atmega328p/tc0/
timsk0.rs1#[doc = "Register `TIMSK0` reader"]
2pub struct R(crate::R<TIMSK0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<TIMSK0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<TIMSK0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<TIMSK0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `TIMSK0` writer"]
17pub struct W(crate::W<TIMSK0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<TIMSK0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<TIMSK0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<TIMSK0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TOIE0` reader - Timer/Counter0 Overflow Interrupt Enable"]
38pub type TOIE0_R = crate::BitReader<bool>;
39#[doc = "Field `TOIE0` writer - Timer/Counter0 Overflow Interrupt Enable"]
40pub type TOIE0_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK0_SPEC, bool, O>;
41#[doc = "Field `OCIE0A` reader - Timer/Counter0 Output Compare Match A Interrupt Enable"]
42pub type OCIE0A_R = crate::BitReader<bool>;
43#[doc = "Field `OCIE0A` writer - Timer/Counter0 Output Compare Match A Interrupt Enable"]
44pub type OCIE0A_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK0_SPEC, bool, O>;
45#[doc = "Field `OCIE0B` reader - Timer/Counter0 Output Compare Match B Interrupt Enable"]
46pub type OCIE0B_R = crate::BitReader<bool>;
47#[doc = "Field `OCIE0B` writer - Timer/Counter0 Output Compare Match B Interrupt Enable"]
48pub type OCIE0B_W<'a, const O: u8> = crate::BitWriter<'a, u8, TIMSK0_SPEC, bool, O>;
49impl R {
50 #[doc = "Bit 0 - Timer/Counter0 Overflow Interrupt Enable"]
51 #[inline(always)]
52 pub fn toie0(&self) -> TOIE0_R {
53 TOIE0_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - Timer/Counter0 Output Compare Match A Interrupt Enable"]
56 #[inline(always)]
57 pub fn ocie0a(&self) -> OCIE0A_R {
58 OCIE0A_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - Timer/Counter0 Output Compare Match B Interrupt Enable"]
61 #[inline(always)]
62 pub fn ocie0b(&self) -> OCIE0B_R {
63 OCIE0B_R::new(((self.bits >> 2) & 1) != 0)
64 }
65}
66impl W {
67 #[doc = "Bit 0 - Timer/Counter0 Overflow Interrupt Enable"]
68 #[inline(always)]
69 #[must_use]
70 pub fn toie0(&mut self) -> TOIE0_W<0> {
71 TOIE0_W::new(self)
72 }
73 #[doc = "Bit 1 - Timer/Counter0 Output Compare Match A Interrupt Enable"]
74 #[inline(always)]
75 #[must_use]
76 pub fn ocie0a(&mut self) -> OCIE0A_W<1> {
77 OCIE0A_W::new(self)
78 }
79 #[doc = "Bit 2 - Timer/Counter0 Output Compare Match B Interrupt Enable"]
80 #[inline(always)]
81 #[must_use]
82 pub fn ocie0b(&mut self) -> OCIE0B_W<2> {
83 OCIE0B_W::new(self)
84 }
85 #[doc = "Writes raw bits to the register."]
86 #[inline(always)]
87 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
88 self.0.bits(bits);
89 self
90 }
91}
92#[doc = "Timer/Counter0 Interrupt Mask Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timsk0](index.html) module"]
93pub struct TIMSK0_SPEC;
94impl crate::RegisterSpec for TIMSK0_SPEC {
95 type Ux = u8;
96}
97#[doc = "`read()` method returns [timsk0::R](R) reader structure"]
98impl crate::Readable for TIMSK0_SPEC {
99 type Reader = R;
100}
101#[doc = "`write(|w| ..)` method takes [timsk0::W](W) writer structure"]
102impl crate::Writable for TIMSK0_SPEC {
103 type Writer = W;
104 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106}
107#[doc = "`reset()` method sets TIMSK0 to value 0"]
108impl crate::Resettable for TIMSK0_SPEC {
109 const RESET_VALUE: Self::Ux = 0;
110}