avr_device/devices/atmega32u4/spi/
spcr.rs

1#[doc = "Register `SPCR` reader"]
2pub struct R(crate::R<SPCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SPCR` writer"]
17pub struct W(crate::W<SPCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SPR` reader - SPI Clock Rate Selects"]
38pub type SPR_R = crate::FieldReader<u8, SPR_A>;
39#[doc = "SPI Clock Rate Selects\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum SPR_A {
43    #[doc = "0: Fosc/4 if SPI2X == 0 else Fosc/2"]
44    FOSC_4_2 = 0,
45    #[doc = "1: Fosc/16 if SPI2X == 0 else Fosc/8"]
46    FOSC_16_8 = 1,
47    #[doc = "2: Fosc/64 if SPI2X == 0 else Fosc/32"]
48    FOSC_64_32 = 2,
49    #[doc = "3: Fosc/128 if SPI2X == 0 else Fosc/64"]
50    FOSC_128_64 = 3,
51}
52impl From<SPR_A> for u8 {
53    #[inline(always)]
54    fn from(variant: SPR_A) -> Self {
55        variant as _
56    }
57}
58impl SPR_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> SPR_A {
62        match self.bits {
63            0 => SPR_A::FOSC_4_2,
64            1 => SPR_A::FOSC_16_8,
65            2 => SPR_A::FOSC_64_32,
66            3 => SPR_A::FOSC_128_64,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `FOSC_4_2`"]
71    #[inline(always)]
72    pub fn is_fosc_4_2(&self) -> bool {
73        *self == SPR_A::FOSC_4_2
74    }
75    #[doc = "Checks if the value of the field is `FOSC_16_8`"]
76    #[inline(always)]
77    pub fn is_fosc_16_8(&self) -> bool {
78        *self == SPR_A::FOSC_16_8
79    }
80    #[doc = "Checks if the value of the field is `FOSC_64_32`"]
81    #[inline(always)]
82    pub fn is_fosc_64_32(&self) -> bool {
83        *self == SPR_A::FOSC_64_32
84    }
85    #[doc = "Checks if the value of the field is `FOSC_128_64`"]
86    #[inline(always)]
87    pub fn is_fosc_128_64(&self) -> bool {
88        *self == SPR_A::FOSC_128_64
89    }
90}
91#[doc = "Field `SPR` writer - SPI Clock Rate Selects"]
92pub type SPR_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, SPCR_SPEC, u8, SPR_A, 2, O>;
93impl<'a, const O: u8> SPR_W<'a, O> {
94    #[doc = "Fosc/4 if SPI2X == 0 else Fosc/2"]
95    #[inline(always)]
96    pub fn fosc_4_2(self) -> &'a mut W {
97        self.variant(SPR_A::FOSC_4_2)
98    }
99    #[doc = "Fosc/16 if SPI2X == 0 else Fosc/8"]
100    #[inline(always)]
101    pub fn fosc_16_8(self) -> &'a mut W {
102        self.variant(SPR_A::FOSC_16_8)
103    }
104    #[doc = "Fosc/64 if SPI2X == 0 else Fosc/32"]
105    #[inline(always)]
106    pub fn fosc_64_32(self) -> &'a mut W {
107        self.variant(SPR_A::FOSC_64_32)
108    }
109    #[doc = "Fosc/128 if SPI2X == 0 else Fosc/64"]
110    #[inline(always)]
111    pub fn fosc_128_64(self) -> &'a mut W {
112        self.variant(SPR_A::FOSC_128_64)
113    }
114}
115#[doc = "Field `CPHA` reader - Clock Phase"]
116pub type CPHA_R = crate::BitReader<bool>;
117#[doc = "Field `CPHA` writer - Clock Phase"]
118pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR_SPEC, bool, O>;
119#[doc = "Field `CPOL` reader - Clock polarity"]
120pub type CPOL_R = crate::BitReader<bool>;
121#[doc = "Field `CPOL` writer - Clock polarity"]
122pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR_SPEC, bool, O>;
123#[doc = "Field `MSTR` reader - Master/Slave Select"]
124pub type MSTR_R = crate::BitReader<bool>;
125#[doc = "Field `MSTR` writer - Master/Slave Select"]
126pub type MSTR_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR_SPEC, bool, O>;
127#[doc = "Field `DORD` reader - Data Order"]
128pub type DORD_R = crate::BitReader<bool>;
129#[doc = "Field `DORD` writer - Data Order"]
130pub type DORD_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR_SPEC, bool, O>;
131#[doc = "Field `SPE` reader - SPI Enable"]
132pub type SPE_R = crate::BitReader<bool>;
133#[doc = "Field `SPE` writer - SPI Enable"]
134pub type SPE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR_SPEC, bool, O>;
135#[doc = "Field `SPIE` reader - SPI Interrupt Enable"]
136pub type SPIE_R = crate::BitReader<bool>;
137#[doc = "Field `SPIE` writer - SPI Interrupt Enable"]
138pub type SPIE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPCR_SPEC, bool, O>;
139impl R {
140    #[doc = "Bits 0:1 - SPI Clock Rate Selects"]
141    #[inline(always)]
142    pub fn spr(&self) -> SPR_R {
143        SPR_R::new(self.bits & 3)
144    }
145    #[doc = "Bit 2 - Clock Phase"]
146    #[inline(always)]
147    pub fn cpha(&self) -> CPHA_R {
148        CPHA_R::new(((self.bits >> 2) & 1) != 0)
149    }
150    #[doc = "Bit 3 - Clock polarity"]
151    #[inline(always)]
152    pub fn cpol(&self) -> CPOL_R {
153        CPOL_R::new(((self.bits >> 3) & 1) != 0)
154    }
155    #[doc = "Bit 4 - Master/Slave Select"]
156    #[inline(always)]
157    pub fn mstr(&self) -> MSTR_R {
158        MSTR_R::new(((self.bits >> 4) & 1) != 0)
159    }
160    #[doc = "Bit 5 - Data Order"]
161    #[inline(always)]
162    pub fn dord(&self) -> DORD_R {
163        DORD_R::new(((self.bits >> 5) & 1) != 0)
164    }
165    #[doc = "Bit 6 - SPI Enable"]
166    #[inline(always)]
167    pub fn spe(&self) -> SPE_R {
168        SPE_R::new(((self.bits >> 6) & 1) != 0)
169    }
170    #[doc = "Bit 7 - SPI Interrupt Enable"]
171    #[inline(always)]
172    pub fn spie(&self) -> SPIE_R {
173        SPIE_R::new(((self.bits >> 7) & 1) != 0)
174    }
175}
176impl W {
177    #[doc = "Bits 0:1 - SPI Clock Rate Selects"]
178    #[inline(always)]
179    #[must_use]
180    pub fn spr(&mut self) -> SPR_W<0> {
181        SPR_W::new(self)
182    }
183    #[doc = "Bit 2 - Clock Phase"]
184    #[inline(always)]
185    #[must_use]
186    pub fn cpha(&mut self) -> CPHA_W<2> {
187        CPHA_W::new(self)
188    }
189    #[doc = "Bit 3 - Clock polarity"]
190    #[inline(always)]
191    #[must_use]
192    pub fn cpol(&mut self) -> CPOL_W<3> {
193        CPOL_W::new(self)
194    }
195    #[doc = "Bit 4 - Master/Slave Select"]
196    #[inline(always)]
197    #[must_use]
198    pub fn mstr(&mut self) -> MSTR_W<4> {
199        MSTR_W::new(self)
200    }
201    #[doc = "Bit 5 - Data Order"]
202    #[inline(always)]
203    #[must_use]
204    pub fn dord(&mut self) -> DORD_W<5> {
205        DORD_W::new(self)
206    }
207    #[doc = "Bit 6 - SPI Enable"]
208    #[inline(always)]
209    #[must_use]
210    pub fn spe(&mut self) -> SPE_W<6> {
211        SPE_W::new(self)
212    }
213    #[doc = "Bit 7 - SPI Interrupt Enable"]
214    #[inline(always)]
215    #[must_use]
216    pub fn spie(&mut self) -> SPIE_W<7> {
217        SPIE_W::new(self)
218    }
219    #[doc = "Writes raw bits to the register."]
220    #[inline(always)]
221    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
222        self.0.bits(bits);
223        self
224    }
225}
226#[doc = "SPI Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spcr](index.html) module"]
227pub struct SPCR_SPEC;
228impl crate::RegisterSpec for SPCR_SPEC {
229    type Ux = u8;
230}
231#[doc = "`read()` method returns [spcr::R](R) reader structure"]
232impl crate::Readable for SPCR_SPEC {
233    type Reader = R;
234}
235#[doc = "`write(|w| ..)` method takes [spcr::W](W) writer structure"]
236impl crate::Writable for SPCR_SPEC {
237    type Writer = W;
238    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
239    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
240}
241#[doc = "`reset()` method sets SPCR to value 0"]
242impl crate::Resettable for SPCR_SPEC {
243    const RESET_VALUE: Self::Ux = 0;
244}
avr_device/devices/atmega32u4/spi/spcr.rs

avr_device/devices/atmega32u4/spi/
spcr.rs
