avr_device/devices/atmega32u4/usart1/
ucsr1a.rs

1#[doc = "Register `UCSR1A` reader"]
2pub struct R(crate::R<UCSR1A_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UCSR1A_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UCSR1A_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UCSR1A_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `UCSR1A` writer"]
17pub struct W(crate::W<UCSR1A_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UCSR1A_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UCSR1A_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UCSR1A_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MPCM1` reader - Multi-processor Communication Mode"]
38pub type MPCM1_R = crate::BitReader<bool>;
39#[doc = "Field `MPCM1` writer - Multi-processor Communication Mode"]
40pub type MPCM1_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1A_SPEC, bool, O>;
41#[doc = "Field `U2X1` reader - Double the USART transmission speed"]
42pub type U2X1_R = crate::BitReader<bool>;
43#[doc = "Field `U2X1` writer - Double the USART transmission speed"]
44pub type U2X1_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1A_SPEC, bool, O>;
45#[doc = "Field `UPE1` reader - Parity Error"]
46pub type UPE1_R = crate::BitReader<bool>;
47#[doc = "Field `DOR1` reader - Data overRun"]
48pub type DOR1_R = crate::BitReader<bool>;
49#[doc = "Field `FE1` reader - Framing Error"]
50pub type FE1_R = crate::BitReader<bool>;
51#[doc = "Field `UDRE1` reader - USART Data Register Empty"]
52pub type UDRE1_R = crate::BitReader<bool>;
53#[doc = "Field `TXC1` reader - USART Transmit Complete"]
54pub type TXC1_R = crate::BitReader<bool>;
55#[doc = "Field `TXC1` writer - USART Transmit Complete"]
56pub type TXC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1A_SPEC, bool, O>;
57#[doc = "Field `RXC1` reader - USART Receive Complete"]
58pub type RXC1_R = crate::BitReader<bool>;
59impl R {
60    #[doc = "Bit 0 - Multi-processor Communication Mode"]
61    #[inline(always)]
62    pub fn mpcm1(&self) -> MPCM1_R {
63        MPCM1_R::new((self.bits & 1) != 0)
64    }
65    #[doc = "Bit 1 - Double the USART transmission speed"]
66    #[inline(always)]
67    pub fn u2x1(&self) -> U2X1_R {
68        U2X1_R::new(((self.bits >> 1) & 1) != 0)
69    }
70    #[doc = "Bit 2 - Parity Error"]
71    #[inline(always)]
72    pub fn upe1(&self) -> UPE1_R {
73        UPE1_R::new(((self.bits >> 2) & 1) != 0)
74    }
75    #[doc = "Bit 3 - Data overRun"]
76    #[inline(always)]
77    pub fn dor1(&self) -> DOR1_R {
78        DOR1_R::new(((self.bits >> 3) & 1) != 0)
79    }
80    #[doc = "Bit 4 - Framing Error"]
81    #[inline(always)]
82    pub fn fe1(&self) -> FE1_R {
83        FE1_R::new(((self.bits >> 4) & 1) != 0)
84    }
85    #[doc = "Bit 5 - USART Data Register Empty"]
86    #[inline(always)]
87    pub fn udre1(&self) -> UDRE1_R {
88        UDRE1_R::new(((self.bits >> 5) & 1) != 0)
89    }
90    #[doc = "Bit 6 - USART Transmit Complete"]
91    #[inline(always)]
92    pub fn txc1(&self) -> TXC1_R {
93        TXC1_R::new(((self.bits >> 6) & 1) != 0)
94    }
95    #[doc = "Bit 7 - USART Receive Complete"]
96    #[inline(always)]
97    pub fn rxc1(&self) -> RXC1_R {
98        RXC1_R::new(((self.bits >> 7) & 1) != 0)
99    }
100}
101impl W {
102    #[doc = "Bit 0 - Multi-processor Communication Mode"]
103    #[inline(always)]
104    #[must_use]
105    pub fn mpcm1(&mut self) -> MPCM1_W<0> {
106        MPCM1_W::new(self)
107    }
108    #[doc = "Bit 1 - Double the USART transmission speed"]
109    #[inline(always)]
110    #[must_use]
111    pub fn u2x1(&mut self) -> U2X1_W<1> {
112        U2X1_W::new(self)
113    }
114    #[doc = "Bit 6 - USART Transmit Complete"]
115    #[inline(always)]
116    #[must_use]
117    pub fn txc1(&mut self) -> TXC1_W<6> {
118        TXC1_W::new(self)
119    }
120    #[doc = "Writes raw bits to the register."]
121    #[inline(always)]
122    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
123        self.0.bits(bits);
124        self
125    }
126}
127#[doc = "USART Control and Status Register A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucsr1a](index.html) module"]
128pub struct UCSR1A_SPEC;
129impl crate::RegisterSpec for UCSR1A_SPEC {
130    type Ux = u8;
131}
132#[doc = "`read()` method returns [ucsr1a::R](R) reader structure"]
133impl crate::Readable for UCSR1A_SPEC {
134    type Reader = R;
135}
136#[doc = "`write(|w| ..)` method takes [ucsr1a::W](W) writer structure"]
137impl crate::Writable for UCSR1A_SPEC {
138    type Writer = W;
139    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
140    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
141}
142#[doc = "`reset()` method sets UCSR1A to value 0"]
143impl crate::Resettable for UCSR1A_SPEC {
144    const RESET_VALUE: Self::Ux = 0;
145}
avr_device/devices/atmega32u4/usart1/ucsr1a.rs

avr_device/devices/atmega32u4/usart1/
ucsr1a.rs
