avr_device/devices/atmega32u4/usart1/
ucsr1c.rs1#[doc = "Register `UCSR1C` reader"]
2pub struct R(crate::R<UCSR1C_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<UCSR1C_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<UCSR1C_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<UCSR1C_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `UCSR1C` writer"]
17pub struct W(crate::W<UCSR1C_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<UCSR1C_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<UCSR1C_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<UCSR1C_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `UCPOL1` reader - Clock Polarity"]
38pub type UCPOL1_R = crate::BitReader<UCPOL1_A>;
39#[doc = "Clock Polarity\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum UCPOL1_A {
42 #[doc = "0: Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"]
43 RISING_EDGE = 0,
44 #[doc = "1: Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"]
45 FALLING_EDGE = 1,
46}
47impl From<UCPOL1_A> for bool {
48 #[inline(always)]
49 fn from(variant: UCPOL1_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl UCPOL1_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> UCPOL1_A {
57 match self.bits {
58 false => UCPOL1_A::RISING_EDGE,
59 true => UCPOL1_A::FALLING_EDGE,
60 }
61 }
62 #[doc = "Checks if the value of the field is `RISING_EDGE`"]
63 #[inline(always)]
64 pub fn is_rising_edge(&self) -> bool {
65 *self == UCPOL1_A::RISING_EDGE
66 }
67 #[doc = "Checks if the value of the field is `FALLING_EDGE`"]
68 #[inline(always)]
69 pub fn is_falling_edge(&self) -> bool {
70 *self == UCPOL1_A::FALLING_EDGE
71 }
72}
73#[doc = "Field `UCPOL1` writer - Clock Polarity"]
74pub type UCPOL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1C_SPEC, UCPOL1_A, O>;
75impl<'a, const O: u8> UCPOL1_W<'a, O> {
76 #[doc = "Transmit on Rising XCKn Edge, Receive on Falling XCKn Edge"]
77 #[inline(always)]
78 pub fn rising_edge(self) -> &'a mut W {
79 self.variant(UCPOL1_A::RISING_EDGE)
80 }
81 #[doc = "Transmit on Falling XCKn Edge, Receive on Rising XCKn Edge"]
82 #[inline(always)]
83 pub fn falling_edge(self) -> &'a mut W {
84 self.variant(UCPOL1_A::FALLING_EDGE)
85 }
86}
87#[doc = "Field `UCSZ1` reader - Character Size"]
88pub type UCSZ1_R = crate::FieldReader<u8, UCSZ1_A>;
89#[doc = "Character Size\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91#[repr(u8)]
92pub enum UCSZ1_A {
93 #[doc = "0: Character Size: 5 bit"]
94 CHR5 = 0,
95 #[doc = "1: Character Size: 6 bit"]
96 CHR6 = 1,
97 #[doc = "2: Character Size: 7 bit"]
98 CHR7 = 2,
99 #[doc = "3: Character Size: 8 bit"]
100 CHR8 = 3,
101}
102impl From<UCSZ1_A> for u8 {
103 #[inline(always)]
104 fn from(variant: UCSZ1_A) -> Self {
105 variant as _
106 }
107}
108impl UCSZ1_R {
109 #[doc = "Get enumerated values variant"]
110 #[inline(always)]
111 pub fn variant(&self) -> UCSZ1_A {
112 match self.bits {
113 0 => UCSZ1_A::CHR5,
114 1 => UCSZ1_A::CHR6,
115 2 => UCSZ1_A::CHR7,
116 3 => UCSZ1_A::CHR8,
117 _ => unreachable!(),
118 }
119 }
120 #[doc = "Checks if the value of the field is `CHR5`"]
121 #[inline(always)]
122 pub fn is_chr5(&self) -> bool {
123 *self == UCSZ1_A::CHR5
124 }
125 #[doc = "Checks if the value of the field is `CHR6`"]
126 #[inline(always)]
127 pub fn is_chr6(&self) -> bool {
128 *self == UCSZ1_A::CHR6
129 }
130 #[doc = "Checks if the value of the field is `CHR7`"]
131 #[inline(always)]
132 pub fn is_chr7(&self) -> bool {
133 *self == UCSZ1_A::CHR7
134 }
135 #[doc = "Checks if the value of the field is `CHR8`"]
136 #[inline(always)]
137 pub fn is_chr8(&self) -> bool {
138 *self == UCSZ1_A::CHR8
139 }
140}
141#[doc = "Field `UCSZ1` writer - Character Size"]
142pub type UCSZ1_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, UCSR1C_SPEC, u8, UCSZ1_A, 2, O>;
143impl<'a, const O: u8> UCSZ1_W<'a, O> {
144 #[doc = "Character Size: 5 bit"]
145 #[inline(always)]
146 pub fn chr5(self) -> &'a mut W {
147 self.variant(UCSZ1_A::CHR5)
148 }
149 #[doc = "Character Size: 6 bit"]
150 #[inline(always)]
151 pub fn chr6(self) -> &'a mut W {
152 self.variant(UCSZ1_A::CHR6)
153 }
154 #[doc = "Character Size: 7 bit"]
155 #[inline(always)]
156 pub fn chr7(self) -> &'a mut W {
157 self.variant(UCSZ1_A::CHR7)
158 }
159 #[doc = "Character Size: 8 bit"]
160 #[inline(always)]
161 pub fn chr8(self) -> &'a mut W {
162 self.variant(UCSZ1_A::CHR8)
163 }
164}
165#[doc = "Field `USBS1` reader - Stop Bit Select"]
166pub type USBS1_R = crate::BitReader<USBS1_A>;
167#[doc = "Stop Bit Select\n\nValue on reset: 0"]
168#[derive(Clone, Copy, Debug, PartialEq, Eq)]
169pub enum USBS1_A {
170 #[doc = "0: 1-bit"]
171 STOP1 = 0,
172 #[doc = "1: 2-bit"]
173 STOP2 = 1,
174}
175impl From<USBS1_A> for bool {
176 #[inline(always)]
177 fn from(variant: USBS1_A) -> Self {
178 variant as u8 != 0
179 }
180}
181impl USBS1_R {
182 #[doc = "Get enumerated values variant"]
183 #[inline(always)]
184 pub fn variant(&self) -> USBS1_A {
185 match self.bits {
186 false => USBS1_A::STOP1,
187 true => USBS1_A::STOP2,
188 }
189 }
190 #[doc = "Checks if the value of the field is `STOP1`"]
191 #[inline(always)]
192 pub fn is_stop1(&self) -> bool {
193 *self == USBS1_A::STOP1
194 }
195 #[doc = "Checks if the value of the field is `STOP2`"]
196 #[inline(always)]
197 pub fn is_stop2(&self) -> bool {
198 *self == USBS1_A::STOP2
199 }
200}
201#[doc = "Field `USBS1` writer - Stop Bit Select"]
202pub type USBS1_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1C_SPEC, USBS1_A, O>;
203impl<'a, const O: u8> USBS1_W<'a, O> {
204 #[doc = "1-bit"]
205 #[inline(always)]
206 pub fn stop1(self) -> &'a mut W {
207 self.variant(USBS1_A::STOP1)
208 }
209 #[doc = "2-bit"]
210 #[inline(always)]
211 pub fn stop2(self) -> &'a mut W {
212 self.variant(USBS1_A::STOP2)
213 }
214}
215#[doc = "Field `UPM1` reader - Parity Mode Bits"]
216pub type UPM1_R = crate::FieldReader<u8, UPM1_A>;
217#[doc = "Parity Mode Bits\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219#[repr(u8)]
220pub enum UPM1_A {
221 #[doc = "0: Disabled"]
222 DISABLED = 0,
223 #[doc = "2: Enabled, Even Parity"]
224 PARITY_EVEN = 2,
225 #[doc = "3: Enabled, Odd Parity"]
226 PARITY_ODD = 3,
227}
228impl From<UPM1_A> for u8 {
229 #[inline(always)]
230 fn from(variant: UPM1_A) -> Self {
231 variant as _
232 }
233}
234impl UPM1_R {
235 #[doc = "Get enumerated values variant"]
236 #[inline(always)]
237 pub fn variant(&self) -> Option<UPM1_A> {
238 match self.bits {
239 0 => Some(UPM1_A::DISABLED),
240 2 => Some(UPM1_A::PARITY_EVEN),
241 3 => Some(UPM1_A::PARITY_ODD),
242 _ => None,
243 }
244 }
245 #[doc = "Checks if the value of the field is `DISABLED`"]
246 #[inline(always)]
247 pub fn is_disabled(&self) -> bool {
248 *self == UPM1_A::DISABLED
249 }
250 #[doc = "Checks if the value of the field is `PARITY_EVEN`"]
251 #[inline(always)]
252 pub fn is_parity_even(&self) -> bool {
253 *self == UPM1_A::PARITY_EVEN
254 }
255 #[doc = "Checks if the value of the field is `PARITY_ODD`"]
256 #[inline(always)]
257 pub fn is_parity_odd(&self) -> bool {
258 *self == UPM1_A::PARITY_ODD
259 }
260}
261#[doc = "Field `UPM1` writer - Parity Mode Bits"]
262pub type UPM1_W<'a, const O: u8> = crate::FieldWriter<'a, u8, UCSR1C_SPEC, u8, UPM1_A, 2, O>;
263impl<'a, const O: u8> UPM1_W<'a, O> {
264 #[doc = "Disabled"]
265 #[inline(always)]
266 pub fn disabled(self) -> &'a mut W {
267 self.variant(UPM1_A::DISABLED)
268 }
269 #[doc = "Enabled, Even Parity"]
270 #[inline(always)]
271 pub fn parity_even(self) -> &'a mut W {
272 self.variant(UPM1_A::PARITY_EVEN)
273 }
274 #[doc = "Enabled, Odd Parity"]
275 #[inline(always)]
276 pub fn parity_odd(self) -> &'a mut W {
277 self.variant(UPM1_A::PARITY_ODD)
278 }
279}
280#[doc = "Field `UMSEL1` reader - USART Mode Select"]
281pub type UMSEL1_R = crate::FieldReader<u8, UMSEL1_A>;
282#[doc = "USART Mode Select\n\nValue on reset: 0"]
283#[derive(Clone, Copy, Debug, PartialEq, Eq)]
284#[repr(u8)]
285pub enum UMSEL1_A {
286 #[doc = "0: Asynchronous USART"]
287 USART_ASYNC = 0,
288 #[doc = "1: Synchronous USART"]
289 USART_SYNC = 1,
290 #[doc = "3: Master SPI (MSPIM)"]
291 SPI_MASTER = 3,
292}
293impl From<UMSEL1_A> for u8 {
294 #[inline(always)]
295 fn from(variant: UMSEL1_A) -> Self {
296 variant as _
297 }
298}
299impl UMSEL1_R {
300 #[doc = "Get enumerated values variant"]
301 #[inline(always)]
302 pub fn variant(&self) -> Option<UMSEL1_A> {
303 match self.bits {
304 0 => Some(UMSEL1_A::USART_ASYNC),
305 1 => Some(UMSEL1_A::USART_SYNC),
306 3 => Some(UMSEL1_A::SPI_MASTER),
307 _ => None,
308 }
309 }
310 #[doc = "Checks if the value of the field is `USART_ASYNC`"]
311 #[inline(always)]
312 pub fn is_usart_async(&self) -> bool {
313 *self == UMSEL1_A::USART_ASYNC
314 }
315 #[doc = "Checks if the value of the field is `USART_SYNC`"]
316 #[inline(always)]
317 pub fn is_usart_sync(&self) -> bool {
318 *self == UMSEL1_A::USART_SYNC
319 }
320 #[doc = "Checks if the value of the field is `SPI_MASTER`"]
321 #[inline(always)]
322 pub fn is_spi_master(&self) -> bool {
323 *self == UMSEL1_A::SPI_MASTER
324 }
325}
326#[doc = "Field `UMSEL1` writer - USART Mode Select"]
327pub type UMSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u8, UCSR1C_SPEC, u8, UMSEL1_A, 2, O>;
328impl<'a, const O: u8> UMSEL1_W<'a, O> {
329 #[doc = "Asynchronous USART"]
330 #[inline(always)]
331 pub fn usart_async(self) -> &'a mut W {
332 self.variant(UMSEL1_A::USART_ASYNC)
333 }
334 #[doc = "Synchronous USART"]
335 #[inline(always)]
336 pub fn usart_sync(self) -> &'a mut W {
337 self.variant(UMSEL1_A::USART_SYNC)
338 }
339 #[doc = "Master SPI (MSPIM)"]
340 #[inline(always)]
341 pub fn spi_master(self) -> &'a mut W {
342 self.variant(UMSEL1_A::SPI_MASTER)
343 }
344}
345impl R {
346 #[doc = "Bit 0 - Clock Polarity"]
347 #[inline(always)]
348 pub fn ucpol1(&self) -> UCPOL1_R {
349 UCPOL1_R::new((self.bits & 1) != 0)
350 }
351 #[doc = "Bits 1:2 - Character Size"]
352 #[inline(always)]
353 pub fn ucsz1(&self) -> UCSZ1_R {
354 UCSZ1_R::new((self.bits >> 1) & 3)
355 }
356 #[doc = "Bit 3 - Stop Bit Select"]
357 #[inline(always)]
358 pub fn usbs1(&self) -> USBS1_R {
359 USBS1_R::new(((self.bits >> 3) & 1) != 0)
360 }
361 #[doc = "Bits 4:5 - Parity Mode Bits"]
362 #[inline(always)]
363 pub fn upm1(&self) -> UPM1_R {
364 UPM1_R::new((self.bits >> 4) & 3)
365 }
366 #[doc = "Bits 6:7 - USART Mode Select"]
367 #[inline(always)]
368 pub fn umsel1(&self) -> UMSEL1_R {
369 UMSEL1_R::new((self.bits >> 6) & 3)
370 }
371}
372impl W {
373 #[doc = "Bit 0 - Clock Polarity"]
374 #[inline(always)]
375 #[must_use]
376 pub fn ucpol1(&mut self) -> UCPOL1_W<0> {
377 UCPOL1_W::new(self)
378 }
379 #[doc = "Bits 1:2 - Character Size"]
380 #[inline(always)]
381 #[must_use]
382 pub fn ucsz1(&mut self) -> UCSZ1_W<1> {
383 UCSZ1_W::new(self)
384 }
385 #[doc = "Bit 3 - Stop Bit Select"]
386 #[inline(always)]
387 #[must_use]
388 pub fn usbs1(&mut self) -> USBS1_W<3> {
389 USBS1_W::new(self)
390 }
391 #[doc = "Bits 4:5 - Parity Mode Bits"]
392 #[inline(always)]
393 #[must_use]
394 pub fn upm1(&mut self) -> UPM1_W<4> {
395 UPM1_W::new(self)
396 }
397 #[doc = "Bits 6:7 - USART Mode Select"]
398 #[inline(always)]
399 #[must_use]
400 pub fn umsel1(&mut self) -> UMSEL1_W<6> {
401 UMSEL1_W::new(self)
402 }
403 #[doc = "Writes raw bits to the register."]
404 #[inline(always)]
405 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
406 self.0.bits(bits);
407 self
408 }
409}
410#[doc = "USART Control and Status Register C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucsr1c](index.html) module"]
411pub struct UCSR1C_SPEC;
412impl crate::RegisterSpec for UCSR1C_SPEC {
413 type Ux = u8;
414}
415#[doc = "`read()` method returns [ucsr1c::R](R) reader structure"]
416impl crate::Readable for UCSR1C_SPEC {
417 type Reader = R;
418}
419#[doc = "`write(|w| ..)` method takes [ucsr1c::W](W) writer structure"]
420impl crate::Writable for UCSR1C_SPEC {
421 type Writer = W;
422 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
423 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
424}
425#[doc = "`reset()` method sets UCSR1C to value 0"]
426impl crate::Resettable for UCSR1C_SPEC {
427 const RESET_VALUE: Self::Ux = 0;
428}