avr_device/devices/atmega32u4/usart1/
ucsr1d.rs

1#[doc = "Register `UCSR1D` reader"]
2pub struct R(crate::R<UCSR1D_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UCSR1D_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UCSR1D_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UCSR1D_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `UCSR1D` writer"]
17pub struct W(crate::W<UCSR1D_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UCSR1D_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UCSR1D_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UCSR1D_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RTSEN` reader - RTS Enable"]
38pub type RTSEN_R = crate::BitReader<bool>;
39#[doc = "Field `RTSEN` writer - RTS Enable"]
40pub type RTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1D_SPEC, bool, O>;
41#[doc = "Field `CTSEN` reader - CTS Enable"]
42pub type CTSEN_R = crate::BitReader<bool>;
43#[doc = "Field `CTSEN` writer - CTS Enable"]
44pub type CTSEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, UCSR1D_SPEC, bool, O>;
45impl R {
46    #[doc = "Bit 0 - RTS Enable"]
47    #[inline(always)]
48    pub fn rtsen(&self) -> RTSEN_R {
49        RTSEN_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1 - CTS Enable"]
52    #[inline(always)]
53    pub fn ctsen(&self) -> CTSEN_R {
54        CTSEN_R::new(((self.bits >> 1) & 1) != 0)
55    }
56}
57impl W {
58    #[doc = "Bit 0 - RTS Enable"]
59    #[inline(always)]
60    #[must_use]
61    pub fn rtsen(&mut self) -> RTSEN_W<0> {
62        RTSEN_W::new(self)
63    }
64    #[doc = "Bit 1 - CTS Enable"]
65    #[inline(always)]
66    #[must_use]
67    pub fn ctsen(&mut self) -> CTSEN_W<1> {
68        CTSEN_W::new(self)
69    }
70    #[doc = "Writes raw bits to the register."]
71    #[inline(always)]
72    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
73        self.0.bits(bits);
74        self
75    }
76}
77#[doc = "USART Control and Status Register D\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ucsr1d](index.html) module"]
78pub struct UCSR1D_SPEC;
79impl crate::RegisterSpec for UCSR1D_SPEC {
80    type Ux = u8;
81}
82#[doc = "`read()` method returns [ucsr1d::R](R) reader structure"]
83impl crate::Readable for UCSR1D_SPEC {
84    type Reader = R;
85}
86#[doc = "`write(|w| ..)` method takes [ucsr1d::W](W) writer structure"]
87impl crate::Writable for UCSR1D_SPEC {
88    type Writer = W;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
91}
92#[doc = "`reset()` method sets UCSR1D to value 0"]
93impl crate::Resettable for UCSR1D_SPEC {
94    const RESET_VALUE: Self::Ux = 0;
95}
avr_device/devices/atmega32u4/usart1/ucsr1d.rs

avr_device/devices/atmega32u4/usart1/
ucsr1d.rs
