avr_device/devices/atmega4809/ccl/
lut2ctrla.rs

1#[doc = "Register `LUT2CTRLA` reader"]
2pub struct R(crate::R<LUT2CTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LUT2CTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LUT2CTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LUT2CTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LUT2CTRLA` writer"]
17pub struct W(crate::W<LUT2CTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LUT2CTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LUT2CTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LUT2CTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENABLE` reader - LUT Enable"]
38pub type ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` writer - LUT Enable"]
40pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, LUT2CTRLA_SPEC, bool, O>;
41#[doc = "Field `CLKSRC` reader - Clock Source Selection"]
42pub type CLKSRC_R = crate::FieldReader<u8, CLKSRC_A>;
43#[doc = "Clock Source Selection\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum CLKSRC_A {
47    #[doc = "0: CLK_PER is clocking the LUT"]
48    CLKPER = 0,
49    #[doc = "1: IN\\[2\\]
50is clocking the LUT"]
51    IN2 = 1,
52    #[doc = "4: 20MHz oscillator before prescaler is clocking the LUT"]
53    OSC20M = 4,
54    #[doc = "5: 32kHz oscillator is clocking the LUT"]
55    OSCULP32K = 5,
56    #[doc = "6: 32kHz oscillator after DIV32 is clocking the LUT"]
57    OSCULP1K = 6,
58}
59impl From<CLKSRC_A> for u8 {
60    #[inline(always)]
61    fn from(variant: CLKSRC_A) -> Self {
62        variant as _
63    }
64}
65impl CLKSRC_R {
66    #[doc = "Get enumerated values variant"]
67    #[inline(always)]
68    pub fn variant(&self) -> Option<CLKSRC_A> {
69        match self.bits {
70            0 => Some(CLKSRC_A::CLKPER),
71            1 => Some(CLKSRC_A::IN2),
72            4 => Some(CLKSRC_A::OSC20M),
73            5 => Some(CLKSRC_A::OSCULP32K),
74            6 => Some(CLKSRC_A::OSCULP1K),
75            _ => None,
76        }
77    }
78    #[doc = "Checks if the value of the field is `CLKPER`"]
79    #[inline(always)]
80    pub fn is_clkper(&self) -> bool {
81        *self == CLKSRC_A::CLKPER
82    }
83    #[doc = "Checks if the value of the field is `IN2`"]
84    #[inline(always)]
85    pub fn is_in2(&self) -> bool {
86        *self == CLKSRC_A::IN2
87    }
88    #[doc = "Checks if the value of the field is `OSC20M`"]
89    #[inline(always)]
90    pub fn is_osc20m(&self) -> bool {
91        *self == CLKSRC_A::OSC20M
92    }
93    #[doc = "Checks if the value of the field is `OSCULP32K`"]
94    #[inline(always)]
95    pub fn is_osculp32k(&self) -> bool {
96        *self == CLKSRC_A::OSCULP32K
97    }
98    #[doc = "Checks if the value of the field is `OSCULP1K`"]
99    #[inline(always)]
100    pub fn is_osculp1k(&self) -> bool {
101        *self == CLKSRC_A::OSCULP1K
102    }
103}
104#[doc = "Field `CLKSRC` writer - Clock Source Selection"]
105pub type CLKSRC_W<'a, const O: u8> = crate::FieldWriter<'a, u8, LUT2CTRLA_SPEC, u8, CLKSRC_A, 3, O>;
106impl<'a, const O: u8> CLKSRC_W<'a, O> {
107    #[doc = "CLK_PER is clocking the LUT"]
108    #[inline(always)]
109    pub fn clkper(self) -> &'a mut W {
110        self.variant(CLKSRC_A::CLKPER)
111    }
112    #[doc = "IN\\[2\\]
113is clocking the LUT"]
114    #[inline(always)]
115    pub fn in2(self) -> &'a mut W {
116        self.variant(CLKSRC_A::IN2)
117    }
118    #[doc = "20MHz oscillator before prescaler is clocking the LUT"]
119    #[inline(always)]
120    pub fn osc20m(self) -> &'a mut W {
121        self.variant(CLKSRC_A::OSC20M)
122    }
123    #[doc = "32kHz oscillator is clocking the LUT"]
124    #[inline(always)]
125    pub fn osculp32k(self) -> &'a mut W {
126        self.variant(CLKSRC_A::OSCULP32K)
127    }
128    #[doc = "32kHz oscillator after DIV32 is clocking the LUT"]
129    #[inline(always)]
130    pub fn osculp1k(self) -> &'a mut W {
131        self.variant(CLKSRC_A::OSCULP1K)
132    }
133}
134#[doc = "Field `FILTSEL` reader - Filter Selection"]
135pub type FILTSEL_R = crate::FieldReader<u8, FILTSEL_A>;
136#[doc = "Filter Selection\n\nValue on reset: 0"]
137#[derive(Clone, Copy, Debug, PartialEq, Eq)]
138#[repr(u8)]
139pub enum FILTSEL_A {
140    #[doc = "0: Filter disabled"]
141    DISABLE = 0,
142    #[doc = "1: Synchronizer enabled"]
143    SYNCH = 1,
144    #[doc = "2: Filter enabled"]
145    FILTER = 2,
146}
147impl From<FILTSEL_A> for u8 {
148    #[inline(always)]
149    fn from(variant: FILTSEL_A) -> Self {
150        variant as _
151    }
152}
153impl FILTSEL_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> Option<FILTSEL_A> {
157        match self.bits {
158            0 => Some(FILTSEL_A::DISABLE),
159            1 => Some(FILTSEL_A::SYNCH),
160            2 => Some(FILTSEL_A::FILTER),
161            _ => None,
162        }
163    }
164    #[doc = "Checks if the value of the field is `DISABLE`"]
165    #[inline(always)]
166    pub fn is_disable(&self) -> bool {
167        *self == FILTSEL_A::DISABLE
168    }
169    #[doc = "Checks if the value of the field is `SYNCH`"]
170    #[inline(always)]
171    pub fn is_synch(&self) -> bool {
172        *self == FILTSEL_A::SYNCH
173    }
174    #[doc = "Checks if the value of the field is `FILTER`"]
175    #[inline(always)]
176    pub fn is_filter(&self) -> bool {
177        *self == FILTSEL_A::FILTER
178    }
179}
180#[doc = "Field `FILTSEL` writer - Filter Selection"]
181pub type FILTSEL_W<'a, const O: u8> =
182    crate::FieldWriter<'a, u8, LUT2CTRLA_SPEC, u8, FILTSEL_A, 2, O>;
183impl<'a, const O: u8> FILTSEL_W<'a, O> {
184    #[doc = "Filter disabled"]
185    #[inline(always)]
186    pub fn disable(self) -> &'a mut W {
187        self.variant(FILTSEL_A::DISABLE)
188    }
189    #[doc = "Synchronizer enabled"]
190    #[inline(always)]
191    pub fn synch(self) -> &'a mut W {
192        self.variant(FILTSEL_A::SYNCH)
193    }
194    #[doc = "Filter enabled"]
195    #[inline(always)]
196    pub fn filter(self) -> &'a mut W {
197        self.variant(FILTSEL_A::FILTER)
198    }
199}
200#[doc = "Field `OUTEN` reader - Output Enable"]
201pub type OUTEN_R = crate::BitReader<bool>;
202#[doc = "Field `OUTEN` writer - Output Enable"]
203pub type OUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, LUT2CTRLA_SPEC, bool, O>;
204#[doc = "Field `EDGEDET` reader - Edge Detection Enable"]
205pub type EDGEDET_R = crate::BitReader<EDGEDET_A>;
206#[doc = "Edge Detection Enable\n\nValue on reset: 0"]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum EDGEDET_A {
209    #[doc = "0: Edge detector is disabled"]
210    DIS = 0,
211    #[doc = "1: Edge detector is enabled"]
212    EN = 1,
213}
214impl From<EDGEDET_A> for bool {
215    #[inline(always)]
216    fn from(variant: EDGEDET_A) -> Self {
217        variant as u8 != 0
218    }
219}
220impl EDGEDET_R {
221    #[doc = "Get enumerated values variant"]
222    #[inline(always)]
223    pub fn variant(&self) -> EDGEDET_A {
224        match self.bits {
225            false => EDGEDET_A::DIS,
226            true => EDGEDET_A::EN,
227        }
228    }
229    #[doc = "Checks if the value of the field is `DIS`"]
230    #[inline(always)]
231    pub fn is_dis(&self) -> bool {
232        *self == EDGEDET_A::DIS
233    }
234    #[doc = "Checks if the value of the field is `EN`"]
235    #[inline(always)]
236    pub fn is_en(&self) -> bool {
237        *self == EDGEDET_A::EN
238    }
239}
240#[doc = "Field `EDGEDET` writer - Edge Detection Enable"]
241pub type EDGEDET_W<'a, const O: u8> = crate::BitWriter<'a, u8, LUT2CTRLA_SPEC, EDGEDET_A, O>;
242impl<'a, const O: u8> EDGEDET_W<'a, O> {
243    #[doc = "Edge detector is disabled"]
244    #[inline(always)]
245    pub fn dis(self) -> &'a mut W {
246        self.variant(EDGEDET_A::DIS)
247    }
248    #[doc = "Edge detector is enabled"]
249    #[inline(always)]
250    pub fn en(self) -> &'a mut W {
251        self.variant(EDGEDET_A::EN)
252    }
253}
254impl R {
255    #[doc = "Bit 0 - LUT Enable"]
256    #[inline(always)]
257    pub fn enable(&self) -> ENABLE_R {
258        ENABLE_R::new((self.bits & 1) != 0)
259    }
260    #[doc = "Bits 1:3 - Clock Source Selection"]
261    #[inline(always)]
262    pub fn clksrc(&self) -> CLKSRC_R {
263        CLKSRC_R::new((self.bits >> 1) & 7)
264    }
265    #[doc = "Bits 4:5 - Filter Selection"]
266    #[inline(always)]
267    pub fn filtsel(&self) -> FILTSEL_R {
268        FILTSEL_R::new((self.bits >> 4) & 3)
269    }
270    #[doc = "Bit 6 - Output Enable"]
271    #[inline(always)]
272    pub fn outen(&self) -> OUTEN_R {
273        OUTEN_R::new(((self.bits >> 6) & 1) != 0)
274    }
275    #[doc = "Bit 7 - Edge Detection Enable"]
276    #[inline(always)]
277    pub fn edgedet(&self) -> EDGEDET_R {
278        EDGEDET_R::new(((self.bits >> 7) & 1) != 0)
279    }
280}
281impl W {
282    #[doc = "Bit 0 - LUT Enable"]
283    #[inline(always)]
284    #[must_use]
285    pub fn enable(&mut self) -> ENABLE_W<0> {
286        ENABLE_W::new(self)
287    }
288    #[doc = "Bits 1:3 - Clock Source Selection"]
289    #[inline(always)]
290    #[must_use]
291    pub fn clksrc(&mut self) -> CLKSRC_W<1> {
292        CLKSRC_W::new(self)
293    }
294    #[doc = "Bits 4:5 - Filter Selection"]
295    #[inline(always)]
296    #[must_use]
297    pub fn filtsel(&mut self) -> FILTSEL_W<4> {
298        FILTSEL_W::new(self)
299    }
300    #[doc = "Bit 6 - Output Enable"]
301    #[inline(always)]
302    #[must_use]
303    pub fn outen(&mut self) -> OUTEN_W<6> {
304        OUTEN_W::new(self)
305    }
306    #[doc = "Bit 7 - Edge Detection Enable"]
307    #[inline(always)]
308    #[must_use]
309    pub fn edgedet(&mut self) -> EDGEDET_W<7> {
310        EDGEDET_W::new(self)
311    }
312    #[doc = "Writes raw bits to the register."]
313    #[inline(always)]
314    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
315        self.0.bits(bits);
316        self
317    }
318}
319#[doc = "LUT Control 2 A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lut2ctrla](index.html) module"]
320pub struct LUT2CTRLA_SPEC;
321impl crate::RegisterSpec for LUT2CTRLA_SPEC {
322    type Ux = u8;
323}
324#[doc = "`read()` method returns [lut2ctrla::R](R) reader structure"]
325impl crate::Readable for LUT2CTRLA_SPEC {
326    type Reader = R;
327}
328#[doc = "`write(|w| ..)` method takes [lut2ctrla::W](W) writer structure"]
329impl crate::Writable for LUT2CTRLA_SPEC {
330    type Writer = W;
331    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
332    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
333}
334#[doc = "`reset()` method sets LUT2CTRLA to value 0"]
335impl crate::Resettable for LUT2CTRLA_SPEC {
336    const RESET_VALUE: Self::Ux = 0;
337}
avr_device/devices/atmega4809/ccl/lut2ctrla.rs

avr_device/devices/atmega4809/ccl/
lut2ctrla.rs
