avr_device/devices/atmega4809/evsys/
channel5.rs1#[doc = "Register `CHANNEL5` reader"]
2pub struct R(crate::R<CHANNEL5_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CHANNEL5_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CHANNEL5_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CHANNEL5_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CHANNEL5` writer"]
17pub struct W(crate::W<CHANNEL5_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CHANNEL5_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CHANNEL5_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CHANNEL5_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `GENERATOR` reader - Generator selector"]
38pub type GENERATOR_R = crate::FieldReader<u8, GENERATOR_A>;
39#[doc = "Generator selector\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum GENERATOR_A {
43 #[doc = "0: Off"]
44 OFF = 0,
45 #[doc = "1: Unified Program and Debug Interface"]
46 UPDI = 1,
47 #[doc = "6: Real Time Counter overflow"]
48 RTC_OVF = 6,
49 #[doc = "7: Real Time Counter compare"]
50 RTC_CMP = 7,
51 #[doc = "8: Periodic Interrupt Timer output 0"]
52 RTC_PIT0 = 8,
53 #[doc = "9: Periodic Interrupt Timer output 1"]
54 RTC_PIT1 = 9,
55 #[doc = "10: Periodic Interrupt Timer output 2"]
56 RTC_PIT2 = 10,
57 #[doc = "11: Periodic Interrupt Timer output 3"]
58 RTC_PIT3 = 11,
59 #[doc = "16: Configurable Custom Logic LUT0"]
60 CCL_LUT0 = 16,
61 #[doc = "17: Configurable Custom Logic LUT1"]
62 CCL_LUT1 = 17,
63 #[doc = "18: Configurable Custom Logic LUT2"]
64 CCL_LUT2 = 18,
65 #[doc = "19: Configurable Custom Logic LUT3"]
66 CCL_LUT3 = 19,
67 #[doc = "32: Analog Comparator 0 out"]
68 AC0_OUT = 32,
69 #[doc = "36: ADC 0 Result Ready Event"]
70 ADC0_RESRDY = 36,
71 #[doc = "64: Port 0 Pin 0"]
72 PORT0_PIN0 = 64,
73 #[doc = "65: Port 0 Pin 1"]
74 PORT0_PIN1 = 65,
75 #[doc = "66: Port 0 Pin 2"]
76 PORT0_PIN2 = 66,
77 #[doc = "67: Port 0 Pin 3"]
78 PORT0_PIN3 = 67,
79 #[doc = "68: Port 0 Pin 4"]
80 PORT0_PIN4 = 68,
81 #[doc = "69: Port 0 Pin 5"]
82 PORT0_PIN5 = 69,
83 #[doc = "70: Port 0 Pin 6"]
84 PORT0_PIN6 = 70,
85 #[doc = "71: Port 0 Pin 7"]
86 PORT0_PIN7 = 71,
87 #[doc = "72: Port 1 Pin 0"]
88 PORT1_PIN0 = 72,
89 #[doc = "73: Port 1 Pin 1"]
90 PORT1_PIN1 = 73,
91 #[doc = "74: Port 1 Pin 2"]
92 PORT1_PIN2 = 74,
93 #[doc = "75: Port 1 Pin 3"]
94 PORT1_PIN3 = 75,
95 #[doc = "76: Port 1 Pin 4"]
96 PORT1_PIN4 = 76,
97 #[doc = "77: Port 1 Pin 5"]
98 PORT1_PIN5 = 77,
99 #[doc = "78: Port 1 Pin 6"]
100 PORT1_PIN6 = 78,
101 #[doc = "79: Port 1 Pin 7"]
102 PORT1_PIN7 = 79,
103 #[doc = "96: USART 0 Xclock"]
104 USART0_XCK = 96,
105 #[doc = "97: USART 1 Xclock"]
106 USART1_XCK = 97,
107 #[doc = "98: USART 2 Xclock"]
108 USART2_XCK = 98,
109 #[doc = "99: USART 3 Xclock"]
110 USART3_XCK = 99,
111 #[doc = "104: SPI 0 Sclock"]
112 SPI0_SCK = 104,
113 #[doc = "128: Timer/Counter A0 overflow / low byte underflow"]
114 TCA0_OVF_LUNF = 128,
115 #[doc = "129: Timer/Counter A0 high byte underflow (split mode)"]
116 TCA0_HUNF = 129,
117 #[doc = "132: Timer/Counter A0 compare 0"]
118 TCA0_CMP0 = 132,
119 #[doc = "133: Timer/Counter A0 compare 1"]
120 TCA0_CMP1 = 133,
121 #[doc = "134: Timer/Counter A0 compare 2"]
122 TCA0_CMP2 = 134,
123 #[doc = "160: Timer/Counter B0 capture"]
124 TCB0_CAPT = 160,
125 #[doc = "162: Timer/Counter B1 capture"]
126 TCB1_CAPT = 162,
127 #[doc = "164: Timer/Counter B2 capture"]
128 TCB2_CAPT = 164,
129 #[doc = "166: Timer/Counter B3 capture"]
130 TCB3_CAPT = 166,
131}
132impl From<GENERATOR_A> for u8 {
133 #[inline(always)]
134 fn from(variant: GENERATOR_A) -> Self {
135 variant as _
136 }
137}
138impl GENERATOR_R {
139 #[doc = "Get enumerated values variant"]
140 #[inline(always)]
141 pub fn variant(&self) -> Option<GENERATOR_A> {
142 match self.bits {
143 0 => Some(GENERATOR_A::OFF),
144 1 => Some(GENERATOR_A::UPDI),
145 6 => Some(GENERATOR_A::RTC_OVF),
146 7 => Some(GENERATOR_A::RTC_CMP),
147 8 => Some(GENERATOR_A::RTC_PIT0),
148 9 => Some(GENERATOR_A::RTC_PIT1),
149 10 => Some(GENERATOR_A::RTC_PIT2),
150 11 => Some(GENERATOR_A::RTC_PIT3),
151 16 => Some(GENERATOR_A::CCL_LUT0),
152 17 => Some(GENERATOR_A::CCL_LUT1),
153 18 => Some(GENERATOR_A::CCL_LUT2),
154 19 => Some(GENERATOR_A::CCL_LUT3),
155 32 => Some(GENERATOR_A::AC0_OUT),
156 36 => Some(GENERATOR_A::ADC0_RESRDY),
157 64 => Some(GENERATOR_A::PORT0_PIN0),
158 65 => Some(GENERATOR_A::PORT0_PIN1),
159 66 => Some(GENERATOR_A::PORT0_PIN2),
160 67 => Some(GENERATOR_A::PORT0_PIN3),
161 68 => Some(GENERATOR_A::PORT0_PIN4),
162 69 => Some(GENERATOR_A::PORT0_PIN5),
163 70 => Some(GENERATOR_A::PORT0_PIN6),
164 71 => Some(GENERATOR_A::PORT0_PIN7),
165 72 => Some(GENERATOR_A::PORT1_PIN0),
166 73 => Some(GENERATOR_A::PORT1_PIN1),
167 74 => Some(GENERATOR_A::PORT1_PIN2),
168 75 => Some(GENERATOR_A::PORT1_PIN3),
169 76 => Some(GENERATOR_A::PORT1_PIN4),
170 77 => Some(GENERATOR_A::PORT1_PIN5),
171 78 => Some(GENERATOR_A::PORT1_PIN6),
172 79 => Some(GENERATOR_A::PORT1_PIN7),
173 96 => Some(GENERATOR_A::USART0_XCK),
174 97 => Some(GENERATOR_A::USART1_XCK),
175 98 => Some(GENERATOR_A::USART2_XCK),
176 99 => Some(GENERATOR_A::USART3_XCK),
177 104 => Some(GENERATOR_A::SPI0_SCK),
178 128 => Some(GENERATOR_A::TCA0_OVF_LUNF),
179 129 => Some(GENERATOR_A::TCA0_HUNF),
180 132 => Some(GENERATOR_A::TCA0_CMP0),
181 133 => Some(GENERATOR_A::TCA0_CMP1),
182 134 => Some(GENERATOR_A::TCA0_CMP2),
183 160 => Some(GENERATOR_A::TCB0_CAPT),
184 162 => Some(GENERATOR_A::TCB1_CAPT),
185 164 => Some(GENERATOR_A::TCB2_CAPT),
186 166 => Some(GENERATOR_A::TCB3_CAPT),
187 _ => None,
188 }
189 }
190 #[doc = "Checks if the value of the field is `OFF`"]
191 #[inline(always)]
192 pub fn is_off(&self) -> bool {
193 *self == GENERATOR_A::OFF
194 }
195 #[doc = "Checks if the value of the field is `UPDI`"]
196 #[inline(always)]
197 pub fn is_updi(&self) -> bool {
198 *self == GENERATOR_A::UPDI
199 }
200 #[doc = "Checks if the value of the field is `RTC_OVF`"]
201 #[inline(always)]
202 pub fn is_rtc_ovf(&self) -> bool {
203 *self == GENERATOR_A::RTC_OVF
204 }
205 #[doc = "Checks if the value of the field is `RTC_CMP`"]
206 #[inline(always)]
207 pub fn is_rtc_cmp(&self) -> bool {
208 *self == GENERATOR_A::RTC_CMP
209 }
210 #[doc = "Checks if the value of the field is `RTC_PIT0`"]
211 #[inline(always)]
212 pub fn is_rtc_pit0(&self) -> bool {
213 *self == GENERATOR_A::RTC_PIT0
214 }
215 #[doc = "Checks if the value of the field is `RTC_PIT1`"]
216 #[inline(always)]
217 pub fn is_rtc_pit1(&self) -> bool {
218 *self == GENERATOR_A::RTC_PIT1
219 }
220 #[doc = "Checks if the value of the field is `RTC_PIT2`"]
221 #[inline(always)]
222 pub fn is_rtc_pit2(&self) -> bool {
223 *self == GENERATOR_A::RTC_PIT2
224 }
225 #[doc = "Checks if the value of the field is `RTC_PIT3`"]
226 #[inline(always)]
227 pub fn is_rtc_pit3(&self) -> bool {
228 *self == GENERATOR_A::RTC_PIT3
229 }
230 #[doc = "Checks if the value of the field is `CCL_LUT0`"]
231 #[inline(always)]
232 pub fn is_ccl_lut0(&self) -> bool {
233 *self == GENERATOR_A::CCL_LUT0
234 }
235 #[doc = "Checks if the value of the field is `CCL_LUT1`"]
236 #[inline(always)]
237 pub fn is_ccl_lut1(&self) -> bool {
238 *self == GENERATOR_A::CCL_LUT1
239 }
240 #[doc = "Checks if the value of the field is `CCL_LUT2`"]
241 #[inline(always)]
242 pub fn is_ccl_lut2(&self) -> bool {
243 *self == GENERATOR_A::CCL_LUT2
244 }
245 #[doc = "Checks if the value of the field is `CCL_LUT3`"]
246 #[inline(always)]
247 pub fn is_ccl_lut3(&self) -> bool {
248 *self == GENERATOR_A::CCL_LUT3
249 }
250 #[doc = "Checks if the value of the field is `AC0_OUT`"]
251 #[inline(always)]
252 pub fn is_ac0_out(&self) -> bool {
253 *self == GENERATOR_A::AC0_OUT
254 }
255 #[doc = "Checks if the value of the field is `ADC0_RESRDY`"]
256 #[inline(always)]
257 pub fn is_adc0_resrdy(&self) -> bool {
258 *self == GENERATOR_A::ADC0_RESRDY
259 }
260 #[doc = "Checks if the value of the field is `PORT0_PIN0`"]
261 #[inline(always)]
262 pub fn is_port0_pin0(&self) -> bool {
263 *self == GENERATOR_A::PORT0_PIN0
264 }
265 #[doc = "Checks if the value of the field is `PORT0_PIN1`"]
266 #[inline(always)]
267 pub fn is_port0_pin1(&self) -> bool {
268 *self == GENERATOR_A::PORT0_PIN1
269 }
270 #[doc = "Checks if the value of the field is `PORT0_PIN2`"]
271 #[inline(always)]
272 pub fn is_port0_pin2(&self) -> bool {
273 *self == GENERATOR_A::PORT0_PIN2
274 }
275 #[doc = "Checks if the value of the field is `PORT0_PIN3`"]
276 #[inline(always)]
277 pub fn is_port0_pin3(&self) -> bool {
278 *self == GENERATOR_A::PORT0_PIN3
279 }
280 #[doc = "Checks if the value of the field is `PORT0_PIN4`"]
281 #[inline(always)]
282 pub fn is_port0_pin4(&self) -> bool {
283 *self == GENERATOR_A::PORT0_PIN4
284 }
285 #[doc = "Checks if the value of the field is `PORT0_PIN5`"]
286 #[inline(always)]
287 pub fn is_port0_pin5(&self) -> bool {
288 *self == GENERATOR_A::PORT0_PIN5
289 }
290 #[doc = "Checks if the value of the field is `PORT0_PIN6`"]
291 #[inline(always)]
292 pub fn is_port0_pin6(&self) -> bool {
293 *self == GENERATOR_A::PORT0_PIN6
294 }
295 #[doc = "Checks if the value of the field is `PORT0_PIN7`"]
296 #[inline(always)]
297 pub fn is_port0_pin7(&self) -> bool {
298 *self == GENERATOR_A::PORT0_PIN7
299 }
300 #[doc = "Checks if the value of the field is `PORT1_PIN0`"]
301 #[inline(always)]
302 pub fn is_port1_pin0(&self) -> bool {
303 *self == GENERATOR_A::PORT1_PIN0
304 }
305 #[doc = "Checks if the value of the field is `PORT1_PIN1`"]
306 #[inline(always)]
307 pub fn is_port1_pin1(&self) -> bool {
308 *self == GENERATOR_A::PORT1_PIN1
309 }
310 #[doc = "Checks if the value of the field is `PORT1_PIN2`"]
311 #[inline(always)]
312 pub fn is_port1_pin2(&self) -> bool {
313 *self == GENERATOR_A::PORT1_PIN2
314 }
315 #[doc = "Checks if the value of the field is `PORT1_PIN3`"]
316 #[inline(always)]
317 pub fn is_port1_pin3(&self) -> bool {
318 *self == GENERATOR_A::PORT1_PIN3
319 }
320 #[doc = "Checks if the value of the field is `PORT1_PIN4`"]
321 #[inline(always)]
322 pub fn is_port1_pin4(&self) -> bool {
323 *self == GENERATOR_A::PORT1_PIN4
324 }
325 #[doc = "Checks if the value of the field is `PORT1_PIN5`"]
326 #[inline(always)]
327 pub fn is_port1_pin5(&self) -> bool {
328 *self == GENERATOR_A::PORT1_PIN5
329 }
330 #[doc = "Checks if the value of the field is `PORT1_PIN6`"]
331 #[inline(always)]
332 pub fn is_port1_pin6(&self) -> bool {
333 *self == GENERATOR_A::PORT1_PIN6
334 }
335 #[doc = "Checks if the value of the field is `PORT1_PIN7`"]
336 #[inline(always)]
337 pub fn is_port1_pin7(&self) -> bool {
338 *self == GENERATOR_A::PORT1_PIN7
339 }
340 #[doc = "Checks if the value of the field is `USART0_XCK`"]
341 #[inline(always)]
342 pub fn is_usart0_xck(&self) -> bool {
343 *self == GENERATOR_A::USART0_XCK
344 }
345 #[doc = "Checks if the value of the field is `USART1_XCK`"]
346 #[inline(always)]
347 pub fn is_usart1_xck(&self) -> bool {
348 *self == GENERATOR_A::USART1_XCK
349 }
350 #[doc = "Checks if the value of the field is `USART2_XCK`"]
351 #[inline(always)]
352 pub fn is_usart2_xck(&self) -> bool {
353 *self == GENERATOR_A::USART2_XCK
354 }
355 #[doc = "Checks if the value of the field is `USART3_XCK`"]
356 #[inline(always)]
357 pub fn is_usart3_xck(&self) -> bool {
358 *self == GENERATOR_A::USART3_XCK
359 }
360 #[doc = "Checks if the value of the field is `SPI0_SCK`"]
361 #[inline(always)]
362 pub fn is_spi0_sck(&self) -> bool {
363 *self == GENERATOR_A::SPI0_SCK
364 }
365 #[doc = "Checks if the value of the field is `TCA0_OVF_LUNF`"]
366 #[inline(always)]
367 pub fn is_tca0_ovf_lunf(&self) -> bool {
368 *self == GENERATOR_A::TCA0_OVF_LUNF
369 }
370 #[doc = "Checks if the value of the field is `TCA0_HUNF`"]
371 #[inline(always)]
372 pub fn is_tca0_hunf(&self) -> bool {
373 *self == GENERATOR_A::TCA0_HUNF
374 }
375 #[doc = "Checks if the value of the field is `TCA0_CMP0`"]
376 #[inline(always)]
377 pub fn is_tca0_cmp0(&self) -> bool {
378 *self == GENERATOR_A::TCA0_CMP0
379 }
380 #[doc = "Checks if the value of the field is `TCA0_CMP1`"]
381 #[inline(always)]
382 pub fn is_tca0_cmp1(&self) -> bool {
383 *self == GENERATOR_A::TCA0_CMP1
384 }
385 #[doc = "Checks if the value of the field is `TCA0_CMP2`"]
386 #[inline(always)]
387 pub fn is_tca0_cmp2(&self) -> bool {
388 *self == GENERATOR_A::TCA0_CMP2
389 }
390 #[doc = "Checks if the value of the field is `TCB0_CAPT`"]
391 #[inline(always)]
392 pub fn is_tcb0_capt(&self) -> bool {
393 *self == GENERATOR_A::TCB0_CAPT
394 }
395 #[doc = "Checks if the value of the field is `TCB1_CAPT`"]
396 #[inline(always)]
397 pub fn is_tcb1_capt(&self) -> bool {
398 *self == GENERATOR_A::TCB1_CAPT
399 }
400 #[doc = "Checks if the value of the field is `TCB2_CAPT`"]
401 #[inline(always)]
402 pub fn is_tcb2_capt(&self) -> bool {
403 *self == GENERATOR_A::TCB2_CAPT
404 }
405 #[doc = "Checks if the value of the field is `TCB3_CAPT`"]
406 #[inline(always)]
407 pub fn is_tcb3_capt(&self) -> bool {
408 *self == GENERATOR_A::TCB3_CAPT
409 }
410}
411#[doc = "Field `GENERATOR` writer - Generator selector"]
412pub type GENERATOR_W<'a, const O: u8> =
413 crate::FieldWriter<'a, u8, CHANNEL5_SPEC, u8, GENERATOR_A, 8, O>;
414impl<'a, const O: u8> GENERATOR_W<'a, O> {
415 #[doc = "Off"]
416 #[inline(always)]
417 pub fn off(self) -> &'a mut W {
418 self.variant(GENERATOR_A::OFF)
419 }
420 #[doc = "Unified Program and Debug Interface"]
421 #[inline(always)]
422 pub fn updi(self) -> &'a mut W {
423 self.variant(GENERATOR_A::UPDI)
424 }
425 #[doc = "Real Time Counter overflow"]
426 #[inline(always)]
427 pub fn rtc_ovf(self) -> &'a mut W {
428 self.variant(GENERATOR_A::RTC_OVF)
429 }
430 #[doc = "Real Time Counter compare"]
431 #[inline(always)]
432 pub fn rtc_cmp(self) -> &'a mut W {
433 self.variant(GENERATOR_A::RTC_CMP)
434 }
435 #[doc = "Periodic Interrupt Timer output 0"]
436 #[inline(always)]
437 pub fn rtc_pit0(self) -> &'a mut W {
438 self.variant(GENERATOR_A::RTC_PIT0)
439 }
440 #[doc = "Periodic Interrupt Timer output 1"]
441 #[inline(always)]
442 pub fn rtc_pit1(self) -> &'a mut W {
443 self.variant(GENERATOR_A::RTC_PIT1)
444 }
445 #[doc = "Periodic Interrupt Timer output 2"]
446 #[inline(always)]
447 pub fn rtc_pit2(self) -> &'a mut W {
448 self.variant(GENERATOR_A::RTC_PIT2)
449 }
450 #[doc = "Periodic Interrupt Timer output 3"]
451 #[inline(always)]
452 pub fn rtc_pit3(self) -> &'a mut W {
453 self.variant(GENERATOR_A::RTC_PIT3)
454 }
455 #[doc = "Configurable Custom Logic LUT0"]
456 #[inline(always)]
457 pub fn ccl_lut0(self) -> &'a mut W {
458 self.variant(GENERATOR_A::CCL_LUT0)
459 }
460 #[doc = "Configurable Custom Logic LUT1"]
461 #[inline(always)]
462 pub fn ccl_lut1(self) -> &'a mut W {
463 self.variant(GENERATOR_A::CCL_LUT1)
464 }
465 #[doc = "Configurable Custom Logic LUT2"]
466 #[inline(always)]
467 pub fn ccl_lut2(self) -> &'a mut W {
468 self.variant(GENERATOR_A::CCL_LUT2)
469 }
470 #[doc = "Configurable Custom Logic LUT3"]
471 #[inline(always)]
472 pub fn ccl_lut3(self) -> &'a mut W {
473 self.variant(GENERATOR_A::CCL_LUT3)
474 }
475 #[doc = "Analog Comparator 0 out"]
476 #[inline(always)]
477 pub fn ac0_out(self) -> &'a mut W {
478 self.variant(GENERATOR_A::AC0_OUT)
479 }
480 #[doc = "ADC 0 Result Ready Event"]
481 #[inline(always)]
482 pub fn adc0_resrdy(self) -> &'a mut W {
483 self.variant(GENERATOR_A::ADC0_RESRDY)
484 }
485 #[doc = "Port 0 Pin 0"]
486 #[inline(always)]
487 pub fn port0_pin0(self) -> &'a mut W {
488 self.variant(GENERATOR_A::PORT0_PIN0)
489 }
490 #[doc = "Port 0 Pin 1"]
491 #[inline(always)]
492 pub fn port0_pin1(self) -> &'a mut W {
493 self.variant(GENERATOR_A::PORT0_PIN1)
494 }
495 #[doc = "Port 0 Pin 2"]
496 #[inline(always)]
497 pub fn port0_pin2(self) -> &'a mut W {
498 self.variant(GENERATOR_A::PORT0_PIN2)
499 }
500 #[doc = "Port 0 Pin 3"]
501 #[inline(always)]
502 pub fn port0_pin3(self) -> &'a mut W {
503 self.variant(GENERATOR_A::PORT0_PIN3)
504 }
505 #[doc = "Port 0 Pin 4"]
506 #[inline(always)]
507 pub fn port0_pin4(self) -> &'a mut W {
508 self.variant(GENERATOR_A::PORT0_PIN4)
509 }
510 #[doc = "Port 0 Pin 5"]
511 #[inline(always)]
512 pub fn port0_pin5(self) -> &'a mut W {
513 self.variant(GENERATOR_A::PORT0_PIN5)
514 }
515 #[doc = "Port 0 Pin 6"]
516 #[inline(always)]
517 pub fn port0_pin6(self) -> &'a mut W {
518 self.variant(GENERATOR_A::PORT0_PIN6)
519 }
520 #[doc = "Port 0 Pin 7"]
521 #[inline(always)]
522 pub fn port0_pin7(self) -> &'a mut W {
523 self.variant(GENERATOR_A::PORT0_PIN7)
524 }
525 #[doc = "Port 1 Pin 0"]
526 #[inline(always)]
527 pub fn port1_pin0(self) -> &'a mut W {
528 self.variant(GENERATOR_A::PORT1_PIN0)
529 }
530 #[doc = "Port 1 Pin 1"]
531 #[inline(always)]
532 pub fn port1_pin1(self) -> &'a mut W {
533 self.variant(GENERATOR_A::PORT1_PIN1)
534 }
535 #[doc = "Port 1 Pin 2"]
536 #[inline(always)]
537 pub fn port1_pin2(self) -> &'a mut W {
538 self.variant(GENERATOR_A::PORT1_PIN2)
539 }
540 #[doc = "Port 1 Pin 3"]
541 #[inline(always)]
542 pub fn port1_pin3(self) -> &'a mut W {
543 self.variant(GENERATOR_A::PORT1_PIN3)
544 }
545 #[doc = "Port 1 Pin 4"]
546 #[inline(always)]
547 pub fn port1_pin4(self) -> &'a mut W {
548 self.variant(GENERATOR_A::PORT1_PIN4)
549 }
550 #[doc = "Port 1 Pin 5"]
551 #[inline(always)]
552 pub fn port1_pin5(self) -> &'a mut W {
553 self.variant(GENERATOR_A::PORT1_PIN5)
554 }
555 #[doc = "Port 1 Pin 6"]
556 #[inline(always)]
557 pub fn port1_pin6(self) -> &'a mut W {
558 self.variant(GENERATOR_A::PORT1_PIN6)
559 }
560 #[doc = "Port 1 Pin 7"]
561 #[inline(always)]
562 pub fn port1_pin7(self) -> &'a mut W {
563 self.variant(GENERATOR_A::PORT1_PIN7)
564 }
565 #[doc = "USART 0 Xclock"]
566 #[inline(always)]
567 pub fn usart0_xck(self) -> &'a mut W {
568 self.variant(GENERATOR_A::USART0_XCK)
569 }
570 #[doc = "USART 1 Xclock"]
571 #[inline(always)]
572 pub fn usart1_xck(self) -> &'a mut W {
573 self.variant(GENERATOR_A::USART1_XCK)
574 }
575 #[doc = "USART 2 Xclock"]
576 #[inline(always)]
577 pub fn usart2_xck(self) -> &'a mut W {
578 self.variant(GENERATOR_A::USART2_XCK)
579 }
580 #[doc = "USART 3 Xclock"]
581 #[inline(always)]
582 pub fn usart3_xck(self) -> &'a mut W {
583 self.variant(GENERATOR_A::USART3_XCK)
584 }
585 #[doc = "SPI 0 Sclock"]
586 #[inline(always)]
587 pub fn spi0_sck(self) -> &'a mut W {
588 self.variant(GENERATOR_A::SPI0_SCK)
589 }
590 #[doc = "Timer/Counter A0 overflow / low byte underflow"]
591 #[inline(always)]
592 pub fn tca0_ovf_lunf(self) -> &'a mut W {
593 self.variant(GENERATOR_A::TCA0_OVF_LUNF)
594 }
595 #[doc = "Timer/Counter A0 high byte underflow (split mode)"]
596 #[inline(always)]
597 pub fn tca0_hunf(self) -> &'a mut W {
598 self.variant(GENERATOR_A::TCA0_HUNF)
599 }
600 #[doc = "Timer/Counter A0 compare 0"]
601 #[inline(always)]
602 pub fn tca0_cmp0(self) -> &'a mut W {
603 self.variant(GENERATOR_A::TCA0_CMP0)
604 }
605 #[doc = "Timer/Counter A0 compare 1"]
606 #[inline(always)]
607 pub fn tca0_cmp1(self) -> &'a mut W {
608 self.variant(GENERATOR_A::TCA0_CMP1)
609 }
610 #[doc = "Timer/Counter A0 compare 2"]
611 #[inline(always)]
612 pub fn tca0_cmp2(self) -> &'a mut W {
613 self.variant(GENERATOR_A::TCA0_CMP2)
614 }
615 #[doc = "Timer/Counter B0 capture"]
616 #[inline(always)]
617 pub fn tcb0_capt(self) -> &'a mut W {
618 self.variant(GENERATOR_A::TCB0_CAPT)
619 }
620 #[doc = "Timer/Counter B1 capture"]
621 #[inline(always)]
622 pub fn tcb1_capt(self) -> &'a mut W {
623 self.variant(GENERATOR_A::TCB1_CAPT)
624 }
625 #[doc = "Timer/Counter B2 capture"]
626 #[inline(always)]
627 pub fn tcb2_capt(self) -> &'a mut W {
628 self.variant(GENERATOR_A::TCB2_CAPT)
629 }
630 #[doc = "Timer/Counter B3 capture"]
631 #[inline(always)]
632 pub fn tcb3_capt(self) -> &'a mut W {
633 self.variant(GENERATOR_A::TCB3_CAPT)
634 }
635}
636impl R {
637 #[doc = "Bits 0:7 - Generator selector"]
638 #[inline(always)]
639 pub fn generator(&self) -> GENERATOR_R {
640 GENERATOR_R::new(self.bits)
641 }
642}
643impl W {
644 #[doc = "Bits 0:7 - Generator selector"]
645 #[inline(always)]
646 #[must_use]
647 pub fn generator(&mut self) -> GENERATOR_W<0> {
648 GENERATOR_W::new(self)
649 }
650 #[doc = "Writes raw bits to the register."]
651 #[inline(always)]
652 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
653 self.0.bits(bits);
654 self
655 }
656}
657#[doc = "Multiplexer Channel 5\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel5](index.html) module"]
658pub struct CHANNEL5_SPEC;
659impl crate::RegisterSpec for CHANNEL5_SPEC {
660 type Ux = u8;
661}
662#[doc = "`read()` method returns [channel5::R](R) reader structure"]
663impl crate::Readable for CHANNEL5_SPEC {
664 type Reader = R;
665}
666#[doc = "`write(|w| ..)` method takes [channel5::W](W) writer structure"]
667impl crate::Writable for CHANNEL5_SPEC {
668 type Writer = W;
669 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
670 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
671}
672#[doc = "`reset()` method sets CHANNEL5 to value 0"]
673impl crate::Resettable for CHANNEL5_SPEC {
674 const RESET_VALUE: Self::Ux = 0;
675}