avr_device/devices/atmega4809/tcb3/
ctrla.rs1#[doc = "Register `CTRLA` reader"]
2pub struct R(crate::R<CTRLA_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRLA_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRLA_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRLA_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRLA` writer"]
17pub struct W(crate::W<CTRLA_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRLA_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRLA_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRLA_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ENABLE` reader - Enable"]
38pub type ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` writer - Enable"]
40pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
41#[doc = "Field `CLKSEL` reader - Clock Select"]
42pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
43#[doc = "Clock Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum CLKSEL_A {
47 #[doc = "0: CLK_PER (No Prescaling)"]
48 CLKDIV1 = 0,
49 #[doc = "1: CLK_PER/2 (From Prescaler)"]
50 CLKDIV2 = 1,
51 #[doc = "2: Use Clock from TCA"]
52 CLKTCA = 2,
53}
54impl From<CLKSEL_A> for u8 {
55 #[inline(always)]
56 fn from(variant: CLKSEL_A) -> Self {
57 variant as _
58 }
59}
60impl CLKSEL_R {
61 #[doc = "Get enumerated values variant"]
62 #[inline(always)]
63 pub fn variant(&self) -> Option<CLKSEL_A> {
64 match self.bits {
65 0 => Some(CLKSEL_A::CLKDIV1),
66 1 => Some(CLKSEL_A::CLKDIV2),
67 2 => Some(CLKSEL_A::CLKTCA),
68 _ => None,
69 }
70 }
71 #[doc = "Checks if the value of the field is `CLKDIV1`"]
72 #[inline(always)]
73 pub fn is_clkdiv1(&self) -> bool {
74 *self == CLKSEL_A::CLKDIV1
75 }
76 #[doc = "Checks if the value of the field is `CLKDIV2`"]
77 #[inline(always)]
78 pub fn is_clkdiv2(&self) -> bool {
79 *self == CLKSEL_A::CLKDIV2
80 }
81 #[doc = "Checks if the value of the field is `CLKTCA`"]
82 #[inline(always)]
83 pub fn is_clktca(&self) -> bool {
84 *self == CLKSEL_A::CLKTCA
85 }
86}
87#[doc = "Field `CLKSEL` writer - Clock Select"]
88pub type CLKSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLA_SPEC, u8, CLKSEL_A, 2, O>;
89impl<'a, const O: u8> CLKSEL_W<'a, O> {
90 #[doc = "CLK_PER (No Prescaling)"]
91 #[inline(always)]
92 pub fn clkdiv1(self) -> &'a mut W {
93 self.variant(CLKSEL_A::CLKDIV1)
94 }
95 #[doc = "CLK_PER/2 (From Prescaler)"]
96 #[inline(always)]
97 pub fn clkdiv2(self) -> &'a mut W {
98 self.variant(CLKSEL_A::CLKDIV2)
99 }
100 #[doc = "Use Clock from TCA"]
101 #[inline(always)]
102 pub fn clktca(self) -> &'a mut W {
103 self.variant(CLKSEL_A::CLKTCA)
104 }
105}
106#[doc = "Field `SYNCUPD` reader - Synchronize Update"]
107pub type SYNCUPD_R = crate::BitReader<bool>;
108#[doc = "Field `SYNCUPD` writer - Synchronize Update"]
109pub type SYNCUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
110#[doc = "Field `RUNSTDBY` reader - Run Standby"]
111pub type RUNSTDBY_R = crate::BitReader<bool>;
112#[doc = "Field `RUNSTDBY` writer - Run Standby"]
113pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>;
114impl R {
115 #[doc = "Bit 0 - Enable"]
116 #[inline(always)]
117 pub fn enable(&self) -> ENABLE_R {
118 ENABLE_R::new((self.bits & 1) != 0)
119 }
120 #[doc = "Bits 1:2 - Clock Select"]
121 #[inline(always)]
122 pub fn clksel(&self) -> CLKSEL_R {
123 CLKSEL_R::new((self.bits >> 1) & 3)
124 }
125 #[doc = "Bit 4 - Synchronize Update"]
126 #[inline(always)]
127 pub fn syncupd(&self) -> SYNCUPD_R {
128 SYNCUPD_R::new(((self.bits >> 4) & 1) != 0)
129 }
130 #[doc = "Bit 6 - Run Standby"]
131 #[inline(always)]
132 pub fn runstdby(&self) -> RUNSTDBY_R {
133 RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0)
134 }
135}
136impl W {
137 #[doc = "Bit 0 - Enable"]
138 #[inline(always)]
139 #[must_use]
140 pub fn enable(&mut self) -> ENABLE_W<0> {
141 ENABLE_W::new(self)
142 }
143 #[doc = "Bits 1:2 - Clock Select"]
144 #[inline(always)]
145 #[must_use]
146 pub fn clksel(&mut self) -> CLKSEL_W<1> {
147 CLKSEL_W::new(self)
148 }
149 #[doc = "Bit 4 - Synchronize Update"]
150 #[inline(always)]
151 #[must_use]
152 pub fn syncupd(&mut self) -> SYNCUPD_W<4> {
153 SYNCUPD_W::new(self)
154 }
155 #[doc = "Bit 6 - Run Standby"]
156 #[inline(always)]
157 #[must_use]
158 pub fn runstdby(&mut self) -> RUNSTDBY_W<6> {
159 RUNSTDBY_W::new(self)
160 }
161 #[doc = "Writes raw bits to the register."]
162 #[inline(always)]
163 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
164 self.0.bits(bits);
165 self
166 }
167}
168#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"]
169pub struct CTRLA_SPEC;
170impl crate::RegisterSpec for CTRLA_SPEC {
171 type Ux = u8;
172}
173#[doc = "`read()` method returns [ctrla::R](R) reader structure"]
174impl crate::Readable for CTRLA_SPEC {
175 type Reader = R;
176}
177#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"]
178impl crate::Writable for CTRLA_SPEC {
179 type Writer = W;
180 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
182}
183#[doc = "`reset()` method sets CTRLA to value 0"]
184impl crate::Resettable for CTRLA_SPEC {
185 const RESET_VALUE: Self::Ux = 0;
186}