avr_device/devices/atmega4809/twi0/
mctrla.rs

1#[doc = "Register `MCTRLA` reader"]
2pub struct R(crate::R<MCTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MCTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MCTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MCTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MCTRLA` writer"]
17pub struct W(crate::W<MCTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MCTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MCTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MCTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ENABLE` reader - Enable TWI Master"]
38pub type ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `ENABLE` writer - Enable TWI Master"]
40pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, MCTRLA_SPEC, bool, O>;
41#[doc = "Field `SMEN` reader - Smart Mode Enable"]
42pub type SMEN_R = crate::BitReader<bool>;
43#[doc = "Field `SMEN` writer - Smart Mode Enable"]
44pub type SMEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, MCTRLA_SPEC, bool, O>;
45#[doc = "Field `TIMEOUT` reader - Inactive Bus Timeout"]
46pub type TIMEOUT_R = crate::FieldReader<u8, TIMEOUT_A>;
47#[doc = "Inactive Bus Timeout\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49#[repr(u8)]
50pub enum TIMEOUT_A {
51    #[doc = "0: Bus Timeout Disabled"]
52    DISABLED = 0,
53    #[doc = "1: 50 Microseconds"]
54    _50US = 1,
55    #[doc = "2: 100 Microseconds"]
56    _100US = 2,
57    #[doc = "3: 200 Microseconds"]
58    _200US = 3,
59}
60impl From<TIMEOUT_A> for u8 {
61    #[inline(always)]
62    fn from(variant: TIMEOUT_A) -> Self {
63        variant as _
64    }
65}
66impl TIMEOUT_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> TIMEOUT_A {
70        match self.bits {
71            0 => TIMEOUT_A::DISABLED,
72            1 => TIMEOUT_A::_50US,
73            2 => TIMEOUT_A::_100US,
74            3 => TIMEOUT_A::_200US,
75            _ => unreachable!(),
76        }
77    }
78    #[doc = "Checks if the value of the field is `DISABLED`"]
79    #[inline(always)]
80    pub fn is_disabled(&self) -> bool {
81        *self == TIMEOUT_A::DISABLED
82    }
83    #[doc = "Checks if the value of the field is `_50US`"]
84    #[inline(always)]
85    pub fn is_50us(&self) -> bool {
86        *self == TIMEOUT_A::_50US
87    }
88    #[doc = "Checks if the value of the field is `_100US`"]
89    #[inline(always)]
90    pub fn is_100us(&self) -> bool {
91        *self == TIMEOUT_A::_100US
92    }
93    #[doc = "Checks if the value of the field is `_200US`"]
94    #[inline(always)]
95    pub fn is_200us(&self) -> bool {
96        *self == TIMEOUT_A::_200US
97    }
98}
99#[doc = "Field `TIMEOUT` writer - Inactive Bus Timeout"]
100pub type TIMEOUT_W<'a, const O: u8> =
101    crate::FieldWriterSafe<'a, u8, MCTRLA_SPEC, u8, TIMEOUT_A, 2, O>;
102impl<'a, const O: u8> TIMEOUT_W<'a, O> {
103    #[doc = "Bus Timeout Disabled"]
104    #[inline(always)]
105    pub fn disabled(self) -> &'a mut W {
106        self.variant(TIMEOUT_A::DISABLED)
107    }
108    #[doc = "50 Microseconds"]
109    #[inline(always)]
110    pub fn _50us(self) -> &'a mut W {
111        self.variant(TIMEOUT_A::_50US)
112    }
113    #[doc = "100 Microseconds"]
114    #[inline(always)]
115    pub fn _100us(self) -> &'a mut W {
116        self.variant(TIMEOUT_A::_100US)
117    }
118    #[doc = "200 Microseconds"]
119    #[inline(always)]
120    pub fn _200us(self) -> &'a mut W {
121        self.variant(TIMEOUT_A::_200US)
122    }
123}
124#[doc = "Field `QCEN` reader - Quick Command Enable"]
125pub type QCEN_R = crate::BitReader<bool>;
126#[doc = "Field `QCEN` writer - Quick Command Enable"]
127pub type QCEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, MCTRLA_SPEC, bool, O>;
128#[doc = "Field `WIEN` reader - Write Interrupt Enable"]
129pub type WIEN_R = crate::BitReader<bool>;
130#[doc = "Field `WIEN` writer - Write Interrupt Enable"]
131pub type WIEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, MCTRLA_SPEC, bool, O>;
132#[doc = "Field `RIEN` reader - Read Interrupt Enable"]
133pub type RIEN_R = crate::BitReader<bool>;
134#[doc = "Field `RIEN` writer - Read Interrupt Enable"]
135pub type RIEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, MCTRLA_SPEC, bool, O>;
136impl R {
137    #[doc = "Bit 0 - Enable TWI Master"]
138    #[inline(always)]
139    pub fn enable(&self) -> ENABLE_R {
140        ENABLE_R::new((self.bits & 1) != 0)
141    }
142    #[doc = "Bit 1 - Smart Mode Enable"]
143    #[inline(always)]
144    pub fn smen(&self) -> SMEN_R {
145        SMEN_R::new(((self.bits >> 1) & 1) != 0)
146    }
147    #[doc = "Bits 2:3 - Inactive Bus Timeout"]
148    #[inline(always)]
149    pub fn timeout(&self) -> TIMEOUT_R {
150        TIMEOUT_R::new((self.bits >> 2) & 3)
151    }
152    #[doc = "Bit 4 - Quick Command Enable"]
153    #[inline(always)]
154    pub fn qcen(&self) -> QCEN_R {
155        QCEN_R::new(((self.bits >> 4) & 1) != 0)
156    }
157    #[doc = "Bit 6 - Write Interrupt Enable"]
158    #[inline(always)]
159    pub fn wien(&self) -> WIEN_R {
160        WIEN_R::new(((self.bits >> 6) & 1) != 0)
161    }
162    #[doc = "Bit 7 - Read Interrupt Enable"]
163    #[inline(always)]
164    pub fn rien(&self) -> RIEN_R {
165        RIEN_R::new(((self.bits >> 7) & 1) != 0)
166    }
167}
168impl W {
169    #[doc = "Bit 0 - Enable TWI Master"]
170    #[inline(always)]
171    #[must_use]
172    pub fn enable(&mut self) -> ENABLE_W<0> {
173        ENABLE_W::new(self)
174    }
175    #[doc = "Bit 1 - Smart Mode Enable"]
176    #[inline(always)]
177    #[must_use]
178    pub fn smen(&mut self) -> SMEN_W<1> {
179        SMEN_W::new(self)
180    }
181    #[doc = "Bits 2:3 - Inactive Bus Timeout"]
182    #[inline(always)]
183    #[must_use]
184    pub fn timeout(&mut self) -> TIMEOUT_W<2> {
185        TIMEOUT_W::new(self)
186    }
187    #[doc = "Bit 4 - Quick Command Enable"]
188    #[inline(always)]
189    #[must_use]
190    pub fn qcen(&mut self) -> QCEN_W<4> {
191        QCEN_W::new(self)
192    }
193    #[doc = "Bit 6 - Write Interrupt Enable"]
194    #[inline(always)]
195    #[must_use]
196    pub fn wien(&mut self) -> WIEN_W<6> {
197        WIEN_W::new(self)
198    }
199    #[doc = "Bit 7 - Read Interrupt Enable"]
200    #[inline(always)]
201    #[must_use]
202    pub fn rien(&mut self) -> RIEN_W<7> {
203        RIEN_W::new(self)
204    }
205    #[doc = "Writes raw bits to the register."]
206    #[inline(always)]
207    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
208        self.0.bits(bits);
209        self
210    }
211}
212#[doc = "Master Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mctrla](index.html) module"]
213pub struct MCTRLA_SPEC;
214impl crate::RegisterSpec for MCTRLA_SPEC {
215    type Ux = u8;
216}
217#[doc = "`read()` method returns [mctrla::R](R) reader structure"]
218impl crate::Readable for MCTRLA_SPEC {
219    type Reader = R;
220}
221#[doc = "`write(|w| ..)` method takes [mctrla::W](W) writer structure"]
222impl crate::Writable for MCTRLA_SPEC {
223    type Writer = W;
224    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
225    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
226}
227#[doc = "`reset()` method sets MCTRLA to value 0"]
228impl crate::Resettable for MCTRLA_SPEC {
229    const RESET_VALUE: Self::Ux = 0;
230}
avr_device/devices/atmega4809/twi0/mctrla.rs

avr_device/devices/atmega4809/twi0/
mctrla.rs
