Expand description
Inter-Integrated Circuit bus
Modules§
- bus_
busy - Bus busy state indicator
- config
- Function configuration register
- data_
read - FIFO read data register
- data_
write - FIFO write data register
- fifo_
config_ 0 - FIFO configuration register 0
- fifo_
config_ 1 - FIFO configuration register 1
- interrupt
- Interrupt enables, states and masks
- period_
data - Duration of data phase
- period_
start - Duration of start phase
- period_
stop - Duration of stop phase
- sub_
address - Register address of slave device
Structs§
- Register
Block - Register block
Type Aliases§
- BUS_
BUSY - bus_busy (rw) register accessor: Bus busy state indicator
- CONFIG
- config (rw) register accessor: Function configuration register
- DATA_
READ - data_read (r) register accessor: FIFO read data register
- DATA_
WRITE - data_write (w) register accessor: FIFO write data register
- FIFO_
CONFIG_ 0 - fifo_config_0 (rw) register accessor: FIFO configuration register 0
- FIFO_
CONFIG_ 1 - fifo_config_1 (rw) register accessor: FIFO configuration register 1
- INTERRUPT
- interrupt (rw) register accessor: Interrupt enables, states and masks
- PERIOD_
DATA - period_data (rw) register accessor: Duration of data phase
- PERIOD_
START - period_start (rw) register accessor: Duration of start phase
- PERIOD_
STOP - period_stop (rw) register accessor: Duration of stop phase
- SUB_
ADDRESS - sub_address (rw) register accessor: Register address of slave device