Expand description
FIFO configuration register 0
Re-exports§
pub use RECEIVE_DMA_R as TRANSMIT_DMA_R;
pub use RECEIVE_DMA_W as TRANSMIT_DMA_W;
pub use RECEIVE_CLEAR_W as TRANSMIT_CLEAR_W;
pub use RECEIVE_OVERFLOW_R as TRANSMIT_OVERFLOW_R;
pub use RECEIVE_UNDERFLOW_R as TRANSMIT_UNDERFLOW_R;
Structs§
- FIFO_
CONFIG_ 0_ SPEC - FIFO configuration register 0
Enums§
- DMA_
ENABLE_ A - Enable signal of receive DMA interface
- FLAG_
CLEAR_ AW - Clears receive FIFO overflow and underflow flags
- HAS_
OVERFLOW_ A - Receive FIFO overflow flag
- HAS_
UNDERFLOW_ A - Receive FIFO underflow flag
Type Aliases§
- LEFT_
JUSTIFIED_ R - Field
left_justified
reader - - LEFT_
JUSTIFIED_ W - Field
left_justified
writer - - MERGE_
LEFT_ RIGHT_ R - Field
merge_left_right
reader - - MERGE_
LEFT_ RIGHT_ W - Field
merge_left_right
writer - - R
- Register
fifo_config_0
reader - RECEIVE_
CLEAR_ W - Field
receive_clear
writer - Clears receive FIFO overflow and underflow flags - RECEIVE_
DMA_ R - Field
receive_dma
reader - Enable signal of receive DMA interface - RECEIVE_
DMA_ W - Field
receive_dma
writer - Enable signal of receive DMA interface - RECEIVE_
OVERFLOW_ R - Field
receive_overflow
reader - Receive FIFO overflow flag - RECEIVE_
UNDERFLOW_ R - Field
receive_underflow
reader - Receive FIFO underflow flag - SWAP_
LEFT_ RIGHT_ R - Field
swap_left_right
reader - - SWAP_
LEFT_ RIGHT_ W - Field
swap_left_right
writer - - W
- Register
fifo_config_0
writer