Module clock_config_0

System clock configuration register 0

Structs

CLOCK_CONFIG_0_SPEC

System clock configuration register 0

Type Aliases

BCLK_DIVIDE_R

Field bclk_divide reader - Set divide factor of bus clock

BCLK_DIVIDE_W

Field bclk_divide writer - Set divide factor of bus clock

BCLK_R

Field bclk reader - Enable or disable bus clock

BCLK_W

Field bclk writer - Enable or disable bus clock

FCLK_R

Field fclk reader - Enable or disable fast clock

FCLK_W

Field fclk writer - Enable or disable fast clock

HCLK_DIVIDE_R

Field hclk_divide reader - Set divide factor of hibernate clock

HCLK_DIVIDE_W

Field hclk_divide writer - Set divide factor of hibernate clock

HCLK_R

Field hclk reader - Enable or disable hibernate clock

HCLK_W

Field hclk writer - Enable or disable hibernate clock

PLL_R

Field pll reader - Enable or disable Phase-Locked Loop

PLL_W

Field pll writer - Enable or disable Phase-Locked Loop

R

Register clock_config_0 reader

ROOT_CLK_SOURCE_R

Field root_clk_source reader - Set source of root clock

ROOT_CLK_SOURCE_W

Field root_clk_source writer - Set source of root clock

W

Register clock_config_0 writer