bl61x_pac/glb/
cgen_cfg1.rs

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#[doc = "Register `cgen_cfg1` reader"]
pub type R = crate::R<CGEN_CFG1_SPEC>;
#[doc = "Register `cgen_cfg1` writer"]
pub type W = crate::W<CGEN_CFG1_SPEC>;
#[doc = "Field `cgen_s1_gpip` reader - "]
pub type CGEN_S1_GPIP_R = crate::BitReader;
#[doc = "Field `cgen_s1_gpip` writer - "]
pub type CGEN_S1_GPIP_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_sec_dbg` reader - "]
pub type CGEN_S1_SEC_DBG_R = crate::BitReader;
#[doc = "Field `cgen_s1_sec_dbg` writer - "]
pub type CGEN_S1_SEC_DBG_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_sec_eng` reader - "]
pub type CGEN_S1_SEC_ENG_R = crate::BitReader;
#[doc = "Field `cgen_s1_sec_eng` writer - "]
pub type CGEN_S1_SEC_ENG_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_tz` reader - "]
pub type CGEN_S1_TZ_R = crate::BitReader;
#[doc = "Field `cgen_s1_tz` writer - "]
pub type CGEN_S1_TZ_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_ef_ctrl` reader - "]
pub type CGEN_S1_EF_CTRL_R = crate::BitReader;
#[doc = "Field `cgen_s1_ef_ctrl` writer - "]
pub type CGEN_S1_EF_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_sf_ctrl` reader - "]
pub type CGEN_S1_SF_CTRL_R = crate::BitReader;
#[doc = "Field `cgen_s1_sf_ctrl` writer - "]
pub type CGEN_S1_SF_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_dma` reader - "]
pub type CGEN_S1_DMA_R = crate::BitReader;
#[doc = "Field `cgen_s1_dma` writer - "]
pub type CGEN_S1_DMA_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1_usb` reader - "]
pub type CGEN_S1_USB_R = crate::BitReader;
#[doc = "Field `cgen_s1_usb` writer - "]
pub type CGEN_S1_USB_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_uart0` reader - "]
pub type CGEN_S1A_UART0_R = crate::BitReader;
#[doc = "Field `cgen_s1a_uart0` writer - "]
pub type CGEN_S1A_UART0_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_uart1` reader - "]
pub type CGEN_S1A_UART1_R = crate::BitReader;
#[doc = "Field `cgen_s1a_uart1` writer - "]
pub type CGEN_S1A_UART1_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_spi` reader - "]
pub type CGEN_S1A_SPI_R = crate::BitReader;
#[doc = "Field `cgen_s1a_spi` writer - "]
pub type CGEN_S1A_SPI_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_i2c` reader - "]
pub type CGEN_S1A_I2C_R = crate::BitReader;
#[doc = "Field `cgen_s1a_i2c` writer - "]
pub type CGEN_S1A_I2C_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_pwm` reader - "]
pub type CGEN_S1A_PWM_R = crate::BitReader;
#[doc = "Field `cgen_s1a_pwm` writer - "]
pub type CGEN_S1A_PWM_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_timer` reader - "]
pub type CGEN_S1A_TIMER_R = crate::BitReader;
#[doc = "Field `cgen_s1a_timer` writer - "]
pub type CGEN_S1A_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_ir` reader - "]
pub type CGEN_S1A_IR_R = crate::BitReader;
#[doc = "Field `cgen_s1a_ir` writer - "]
pub type CGEN_S1A_IR_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_cks` reader - "]
pub type CGEN_S1A_CKS_R = crate::BitReader;
#[doc = "Field `cgen_s1a_cks` writer - "]
pub type CGEN_S1A_CKS_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_dbi` reader - "]
pub type CGEN_S1A_DBI_R = crate::BitReader;
#[doc = "Field `cgen_s1a_dbi` writer - "]
pub type CGEN_S1A_DBI_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_i2c1` reader - "]
pub type CGEN_S1A_I2C1_R = crate::BitReader;
#[doc = "Field `cgen_s1a_i2c1` writer - "]
pub type CGEN_S1A_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_uart2` reader - "]
pub type CGEN_S1A_UART2_R = crate::BitReader;
#[doc = "Field `cgen_s1a_uart2` writer - "]
pub type CGEN_S1A_UART2_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `cgen_s1a_i2s` reader - "]
pub type CGEN_S1A_I2S_R = crate::BitReader;
#[doc = "Field `cgen_s1a_i2s` writer - "]
pub type CGEN_S1A_I2S_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 2"]
    #[inline(always)]
    pub fn cgen_s1_gpip(&self) -> CGEN_S1_GPIP_R {
        CGEN_S1_GPIP_R::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    pub fn cgen_s1_sec_dbg(&self) -> CGEN_S1_SEC_DBG_R {
        CGEN_S1_SEC_DBG_R::new(((self.bits >> 3) & 1) != 0)
    }
    #[doc = "Bit 4"]
    #[inline(always)]
    pub fn cgen_s1_sec_eng(&self) -> CGEN_S1_SEC_ENG_R {
        CGEN_S1_SEC_ENG_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5"]
    #[inline(always)]
    pub fn cgen_s1_tz(&self) -> CGEN_S1_TZ_R {
        CGEN_S1_TZ_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 7"]
    #[inline(always)]
    pub fn cgen_s1_ef_ctrl(&self) -> CGEN_S1_EF_CTRL_R {
        CGEN_S1_EF_CTRL_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 11"]
    #[inline(always)]
    pub fn cgen_s1_sf_ctrl(&self) -> CGEN_S1_SF_CTRL_R {
        CGEN_S1_SF_CTRL_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    pub fn cgen_s1_dma(&self) -> CGEN_S1_DMA_R {
        CGEN_S1_DMA_R::new(((self.bits >> 12) & 1) != 0)
    }
    #[doc = "Bit 13"]
    #[inline(always)]
    pub fn cgen_s1_usb(&self) -> CGEN_S1_USB_R {
        CGEN_S1_USB_R::new(((self.bits >> 13) & 1) != 0)
    }
    #[doc = "Bit 16"]
    #[inline(always)]
    pub fn cgen_s1a_uart0(&self) -> CGEN_S1A_UART0_R {
        CGEN_S1A_UART0_R::new(((self.bits >> 16) & 1) != 0)
    }
    #[doc = "Bit 17"]
    #[inline(always)]
    pub fn cgen_s1a_uart1(&self) -> CGEN_S1A_UART1_R {
        CGEN_S1A_UART1_R::new(((self.bits >> 17) & 1) != 0)
    }
    #[doc = "Bit 18"]
    #[inline(always)]
    pub fn cgen_s1a_spi(&self) -> CGEN_S1A_SPI_R {
        CGEN_S1A_SPI_R::new(((self.bits >> 18) & 1) != 0)
    }
    #[doc = "Bit 19"]
    #[inline(always)]
    pub fn cgen_s1a_i2c(&self) -> CGEN_S1A_I2C_R {
        CGEN_S1A_I2C_R::new(((self.bits >> 19) & 1) != 0)
    }
    #[doc = "Bit 20"]
    #[inline(always)]
    pub fn cgen_s1a_pwm(&self) -> CGEN_S1A_PWM_R {
        CGEN_S1A_PWM_R::new(((self.bits >> 20) & 1) != 0)
    }
    #[doc = "Bit 21"]
    #[inline(always)]
    pub fn cgen_s1a_timer(&self) -> CGEN_S1A_TIMER_R {
        CGEN_S1A_TIMER_R::new(((self.bits >> 21) & 1) != 0)
    }
    #[doc = "Bit 22"]
    #[inline(always)]
    pub fn cgen_s1a_ir(&self) -> CGEN_S1A_IR_R {
        CGEN_S1A_IR_R::new(((self.bits >> 22) & 1) != 0)
    }
    #[doc = "Bit 23"]
    #[inline(always)]
    pub fn cgen_s1a_cks(&self) -> CGEN_S1A_CKS_R {
        CGEN_S1A_CKS_R::new(((self.bits >> 23) & 1) != 0)
    }
    #[doc = "Bit 24"]
    #[inline(always)]
    pub fn cgen_s1a_dbi(&self) -> CGEN_S1A_DBI_R {
        CGEN_S1A_DBI_R::new(((self.bits >> 24) & 1) != 0)
    }
    #[doc = "Bit 25"]
    #[inline(always)]
    pub fn cgen_s1a_i2c1(&self) -> CGEN_S1A_I2C1_R {
        CGEN_S1A_I2C1_R::new(((self.bits >> 25) & 1) != 0)
    }
    #[doc = "Bit 26"]
    #[inline(always)]
    pub fn cgen_s1a_uart2(&self) -> CGEN_S1A_UART2_R {
        CGEN_S1A_UART2_R::new(((self.bits >> 26) & 1) != 0)
    }
    #[doc = "Bit 27"]
    #[inline(always)]
    pub fn cgen_s1a_i2s(&self) -> CGEN_S1A_I2S_R {
        CGEN_S1A_I2S_R::new(((self.bits >> 27) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 2"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_gpip(&mut self) -> CGEN_S1_GPIP_W<CGEN_CFG1_SPEC> {
        CGEN_S1_GPIP_W::new(self, 2)
    }
    #[doc = "Bit 3"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_sec_dbg(&mut self) -> CGEN_S1_SEC_DBG_W<CGEN_CFG1_SPEC> {
        CGEN_S1_SEC_DBG_W::new(self, 3)
    }
    #[doc = "Bit 4"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_sec_eng(&mut self) -> CGEN_S1_SEC_ENG_W<CGEN_CFG1_SPEC> {
        CGEN_S1_SEC_ENG_W::new(self, 4)
    }
    #[doc = "Bit 5"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_tz(&mut self) -> CGEN_S1_TZ_W<CGEN_CFG1_SPEC> {
        CGEN_S1_TZ_W::new(self, 5)
    }
    #[doc = "Bit 7"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_ef_ctrl(&mut self) -> CGEN_S1_EF_CTRL_W<CGEN_CFG1_SPEC> {
        CGEN_S1_EF_CTRL_W::new(self, 7)
    }
    #[doc = "Bit 11"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_sf_ctrl(&mut self) -> CGEN_S1_SF_CTRL_W<CGEN_CFG1_SPEC> {
        CGEN_S1_SF_CTRL_W::new(self, 11)
    }
    #[doc = "Bit 12"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_dma(&mut self) -> CGEN_S1_DMA_W<CGEN_CFG1_SPEC> {
        CGEN_S1_DMA_W::new(self, 12)
    }
    #[doc = "Bit 13"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1_usb(&mut self) -> CGEN_S1_USB_W<CGEN_CFG1_SPEC> {
        CGEN_S1_USB_W::new(self, 13)
    }
    #[doc = "Bit 16"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_uart0(&mut self) -> CGEN_S1A_UART0_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_UART0_W::new(self, 16)
    }
    #[doc = "Bit 17"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_uart1(&mut self) -> CGEN_S1A_UART1_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_UART1_W::new(self, 17)
    }
    #[doc = "Bit 18"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_spi(&mut self) -> CGEN_S1A_SPI_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_SPI_W::new(self, 18)
    }
    #[doc = "Bit 19"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_i2c(&mut self) -> CGEN_S1A_I2C_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_I2C_W::new(self, 19)
    }
    #[doc = "Bit 20"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_pwm(&mut self) -> CGEN_S1A_PWM_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_PWM_W::new(self, 20)
    }
    #[doc = "Bit 21"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_timer(&mut self) -> CGEN_S1A_TIMER_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_TIMER_W::new(self, 21)
    }
    #[doc = "Bit 22"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_ir(&mut self) -> CGEN_S1A_IR_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_IR_W::new(self, 22)
    }
    #[doc = "Bit 23"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_cks(&mut self) -> CGEN_S1A_CKS_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_CKS_W::new(self, 23)
    }
    #[doc = "Bit 24"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_dbi(&mut self) -> CGEN_S1A_DBI_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_DBI_W::new(self, 24)
    }
    #[doc = "Bit 25"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_i2c1(&mut self) -> CGEN_S1A_I2C1_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_I2C1_W::new(self, 25)
    }
    #[doc = "Bit 26"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_uart2(&mut self) -> CGEN_S1A_UART2_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_UART2_W::new(self, 26)
    }
    #[doc = "Bit 27"]
    #[inline(always)]
    #[must_use]
    pub fn cgen_s1a_i2s(&mut self) -> CGEN_S1A_I2S_W<CGEN_CFG1_SPEC> {
        CGEN_S1A_I2S_W::new(self, 27)
    }
    #[doc = r" Writes raw bits to the register."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
}
#[doc = "cgen_s1a + cgen_s1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgen_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgen_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CGEN_CFG1_SPEC;
impl crate::RegisterSpec for CGEN_CFG1_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`cgen_cfg1::R`](R) reader structure"]
impl crate::Readable for CGEN_CFG1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cgen_cfg1::W`](W) writer structure"]
impl crate::Writable for CGEN_CFG1_SPEC {
    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets cgen_cfg1 to value 0"]
impl crate::Resettable for CGEN_CFG1_SPEC {
    const RESET_VALUE: Self::Ux = 0;
}