Enum capstone::arch::arm64::Arm64OperandType [−][src]
pub enum Arm64OperandType { Reg(RegId), Imm(i64), Mem(Arm64OpMem), Fp(f64), Cimm(i64), RegMrs(Arm64Sysreg), RegMsr(Arm64Sysreg), Pstate(Arm64Pstate), Sys(u32), Prefetch(ArmPrefetchOp), Barrier(Arm64BarrierOp), Invalid, }
Expand description
ARM64 operand
Variants
Reg(RegId)
Register
Immediate
Mem(Arm64OpMem)
Memory
Floating point
C-IMM
RegMrs(Arm64Sysreg)
System register MRS (move the contents of a PSR to a general-purpose register)
RegMsr(Arm64Sysreg)
System register MSR (move to system coprocessor register from ARM register)
Pstate(Arm64Pstate)
System PState Field (MSR instruction)
IC/DC/AT/TLBI operation (see Arm64IcOp, Arm64DcOp, Arm64AtOp, Arm64TlbiOp)
Prefetch(ArmPrefetchOp)
PRFM operation
Barrier(Arm64BarrierOp)
Memory barrier operation (ISB/DMB/DSB instructions)
Invalid
Trait Implementations
This method tests for self
and other
values to be equal, and is used
by ==
. Read more
This method tests for !=
.
Auto Trait Implementations
Blanket Implementations
Mutably borrows from an owned value. Read more