cortex_m/peripheral/
tpiu.rs

1//! Trace Port Interface Unit;
2//!
3//! *NOTE* Not available on Armv6-M.
4
5use volatile_register::{RO, RW, WO};
6
7/// Register block
8#[repr(C)]
9pub struct RegisterBlock {
10    /// Supported Parallel Port Sizes
11    pub sspsr: RO<u32>,
12    /// Current Parallel Port Size
13    pub cspsr: RW<u32>,
14    reserved0: [u32; 2],
15    /// Asynchronous Clock Prescaler
16    pub acpr: RW<u32>,
17    reserved1: [u32; 55],
18    /// Selected Pin Control
19    pub sppr: RW<u32>,
20    reserved2: [u32; 132],
21    /// Formatter and Flush Control
22    pub ffcr: RW<u32>,
23    reserved3: [u32; 810],
24    /// Lock Access
25    pub lar: WO<u32>,
26    /// Lock Status
27    pub lsr: RO<u32>,
28    reserved4: [u32; 4],
29    /// TPIU Type
30    pub _type: RO<u32>,
31}
cortex_m/peripheral/tpiu.rs

cortex_m/peripheral/
tpiu.rs
