cortex_m/peripheral/
icb.rs

1//! Implementation Control Block
2
3#[cfg(any(armv7m, armv8m, native))]
4use volatile_register::RO;
5use volatile_register::RW;
6
7/// Register block
8#[repr(C)]
9pub struct RegisterBlock {
10    /// Interrupt Controller Type Register
11    ///
12    /// The bottom four bits of this register give the number of implemented
13    /// interrupt lines, divided by 32. So a value of `0b0010` indicates 64
14    /// interrupts.
15    #[cfg(any(armv7m, armv8m, native))]
16    pub ictr: RO<u32>,
17
18    /// The ICTR is not defined in the ARMv6-M Architecture Reference manual, so
19    /// we replace it with this.
20    #[cfg(not(any(armv7m, armv8m, native)))]
21    _reserved: u32,
22
23    /// Auxiliary Control Register
24    ///
25    /// This register is entirely implementation defined -- the standard gives
26    /// it an address, but does not define its role or contents.
27    pub actlr: RW<u32>,
28
29    /// Coprocessor Power Control Register
30    #[cfg(armv8m)]
31    pub cppwr: RW<u32>,
32}
cortex_m/peripheral/icb.rs

cortex_m/peripheral/
icb.rs
