cortex_m

Module peripheral

Source
Expand description

Core peripherals.

§API

To use (most of) the peripheral API first you must get an instance of the peripheral. All the core peripherals are modeled as singletons (there can only ever be, at most, one instance of any one of them at any given point in time) and the only way to get an instance of them is through the Peripherals::take method.

let mut peripherals = Peripherals::take().unwrap();
peripherals.DCB.enable_trace();

This method can only be successfully called once – this is why the method returns an Option. Subsequent calls to the method will result in a None value being returned.

ⓘ
let ok = Peripherals::take().unwrap();
let panics = Peripherals::take().unwrap();

A part of the peripheral API doesn’t require access to a peripheral instance. This part of the API is provided as static methods on the peripheral types. One example is the DWT::cycle_count method.

{
    let mut peripherals = Peripherals::take().unwrap();
    peripherals.DCB.enable_trace();
    peripherals.DWT.enable_cycle_counter();
} // all the peripheral singletons are destroyed here

// but this method can be called without a DWT instance
let cyccnt = DWT::cycle_count();

The singleton property can be unsafely bypassed using the ptr static method which is available on all the peripheral types. This method is a useful building block for implementing safe higher level abstractions.

{
    let mut peripherals = Peripherals::take().unwrap();
    peripherals.DCB.enable_trace();
    peripherals.DWT.enable_cycle_counter();
} // all the peripheral singletons are destroyed here

// actually safe because this is an atomic read with no side effects
let cyccnt = unsafe { (*DWT::PTR).cyccnt.read() };

§References

  • ARMv7-M Architecture Reference Manual (Issue E.b) - Chapter B3

Modules§

cbp
Cache and branch predictor maintenance operations
cpuid
CPUID
dcb
Debug Control Block
dwt
Data Watchpoint and Trace unit
fpb
Flash Patch and Breakpoint unit
icb
Implementation Control Block
mpu
Memory Protection Unit
nvic
Nested Vector Interrupt Controller
sau
Security Attribution Unit
scb
System Control Block
syst
SysTick: System Timer
tpiu
Trace Port Interface Unit;

Structs§

CBP
Cache and branch predictor maintenance operations
CPUID
CPUID
DCB
Debug Control Block
DWT
Data Watchpoint and Trace unit
FPB
Flash Patch and Breakpoint unit
FPU
Floating Point Unit
ICB
Implementation Control Block.
ITM
Instrumentation Trace Macrocell
MPU
Memory Protection Unit
NVIC
Nested Vector Interrupt Controller
Peripherals
Core peripherals
SAU
Security Attribution Unit
SCB
System Control Block
SYST
SysTick: System Timer
TPIU
Trace Port Interface Unit