1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};

pub(crate) fn define() -> SettingGroup {
    let mut settings = SettingGroupBuilder::new("shared");

    settings.add_enum(
        "regalloc",
        r#"Register allocator to use with the MachInst backend.

        This selects the register allocator as an option among those offered by the `regalloc.rs`
        crate. Please report register allocation bugs to the maintainers of this crate whenever
        possible.

        Note: this only applies to target that use the MachInst backend. As of 2020-04-17, this
        means the x86_64 backend doesn't use this yet.

        Possible values:

        - `backtracking` is a greedy, backtracking register allocator as implemented in
        Spidermonkey's optimizing tier IonMonkey. It may take more time to allocate registers, but
        it should generate better code in general, resulting in better throughput of generated
        code.
        - `backtracking_checked` is the backtracking allocator with additional self checks that may
        take some time to run, and thus these checks are disabled by default.
        - `experimental_linear_scan` is an experimental linear scan allocator. It may take less
        time to allocate registers, but generated code's quality may be inferior. As of
        2020-04-17, it is still experimental and it should not be used in production settings.
        - `experimental_linear_scan_checked` is the linear scan allocator with additional self
        checks that may take some time to run, and thus these checks are disabled by default.
    "#,
        vec![
            "backtracking",
            "backtracking_checked",
            "experimental_linear_scan",
            "experimental_linear_scan_checked",
        ],
    );

    settings.add_enum(
        "opt_level",
        r#"
        Optimization level:

        - none: Minimise compile time by disabling most optimizations.
        - speed: Generate the fastest possible code
        - speed_and_size: like "speed", but also perform transformations
          aimed at reducing code size.
        "#,
        vec!["none", "speed", "speed_and_size"],
    );

    settings.add_bool(
        "enable_verifier",
        r#"
        Run the Cranelift IR verifier at strategic times during compilation.

        This makes compilation slower but catches many bugs. The verifier is always enabled by
        default, which is useful during development.
        "#,
        true,
    );

    // Note that Cranelift doesn't currently need an is_pie flag, because PIE is
    // just PIC where symbols can't be pre-empted, which can be expressed with the
    // `colocated` flag on external functions and global values.
    settings.add_bool(
        "is_pic",
        "Enable Position-Independent Code generation",
        false,
    );

    settings.add_bool(
        "use_colocated_libcalls",
        r#"
            Use colocated libcalls.

            Generate code that assumes that libcalls can be declared "colocated",
            meaning they will be defined along with the current function, such that
            they can use more efficient addressing.
            "#,
        false,
    );

    settings.add_bool(
        "avoid_div_traps",
        r#"
            Generate explicit checks around native division instructions to avoid
            their trapping.

            This is primarily used by SpiderMonkey which doesn't install a signal
            handler for SIGFPE, but expects a SIGILL trap for division by zero.

            On ISAs like ARM where the native division instructions don't trap,
            this setting has no effect - explicit checks are always inserted.
            "#,
        false,
    );

    settings.add_bool(
        "enable_float",
        r#"
            Enable the use of floating-point instructions

            Disabling use of floating-point instructions is not yet implemented.
            "#,
        true,
    );

    settings.add_bool(
        "enable_nan_canonicalization",
        r#"
            Enable NaN canonicalization

            This replaces NaNs with a single canonical value, for users requiring
            entirely deterministic WebAssembly computation. This is not required
            by the WebAssembly spec, so it is not enabled by default.
            "#,
        false,
    );

    settings.add_bool(
        "enable_pinned_reg",
        r#"Enable the use of the pinned register.

        This register is excluded from register allocation, and is completely under the control of
        the end-user. It is possible to read it via the get_pinned_reg instruction, and to set it
        with the set_pinned_reg instruction.
        "#,
        false,
    );

    settings.add_bool(
        "use_pinned_reg_as_heap_base",
        r#"Use the pinned register as the heap base.

        Enabling this requires the enable_pinned_reg setting to be set to true. It enables a custom
        legalization of the `heap_addr` instruction so it will use the pinned register as the heap
        base, instead of fetching it from a global value.

        Warning! Enabling this means that the pinned register *must* be maintained to contain the
        heap base address at all times, during the lifetime of a function. Using the pinned
        register for other purposes when this is set is very likely to cause crashes.
        "#,
        false,
    );

    settings.add_bool("enable_simd", "Enable the use of SIMD instructions.", false);

    settings.add_bool(
        "enable_atomics",
        "Enable the use of atomic instructions",
        true,
    );

    settings.add_bool(
        "enable_safepoints",
        r#"
            Enable safepoint instruction insertions.

            This will allow the emit_stackmaps() function to insert the safepoint
            instruction on top of calls and interrupt traps in order to display the
            live reference values at that point in the program.
            "#,
        false,
    );

    settings.add_enum(
        "tls_model",
        r#"
            Defines the model used to perform TLS accesses.
        "#,
        vec!["none", "elf_gd", "macho", "coff"],
    );

    // Settings specific to the `baldrdash` calling convention.

    settings.add_enum(
        "libcall_call_conv",
        r#"
            Defines the calling convention to use for LibCalls call expansion,
            since it may be different from the ISA default calling convention.

            The default value is to use the same calling convention as the ISA
            default calling convention.

            This list should be kept in sync with the list of calling
            conventions available in isa/call_conv.rs.
        "#,
        vec![
            "isa_default",
            "fast",
            "cold",
            "system_v",
            "windows_fastcall",
            "baldrdash_system_v",
            "baldrdash_windows",
            "probestack",
        ],
    );

    settings.add_num(
        "baldrdash_prologue_words",
        r#"
            Number of pointer-sized words pushed by the baldrdash prologue.

            Functions with the `baldrdash` calling convention don't generate their
            own prologue and epilogue. They depend on externally generated code
            that pushes a fixed number of words in the prologue and restores them
            in the epilogue.

            This setting configures the number of pointer-sized words pushed on the
            stack when the Cranelift-generated code is entered. This includes the
            pushed return address on x86.
            "#,
        0,
    );

    // BaldrMonkey requires that not-yet-relocated function addresses be encoded
    // as all-ones bitpatterns.
    settings.add_bool(
        "emit_all_ones_funcaddrs",
        "Emit not-yet-relocated function addresses as all-ones bit patterns.",
        false,
    );

    // Stack probing options.

    settings.add_bool(
        "enable_probestack",
        r#"
            Enable the use of stack probes, for calling conventions which support this
            functionality.
            "#,
        true,
    );

    settings.add_bool(
        "probestack_func_adjusts_sp",
        r#"
            Set this to true of the stack probe function modifies the stack pointer
            itself.
            "#,
        false,
    );

    settings.add_num(
        "probestack_size_log2",
        r#"
            The log2 of the size of the stack guard region.

            Stack frames larger than this size will have stack overflow checked
            by calling the probestack function.

            The default is 12, which translates to a size of 4096.
            "#,
        12,
    );

    // Jump table options.

    settings.add_bool(
        "enable_jump_tables",
        "Enable the use of jump tables in generated machine code.",
        true,
    );

    settings.build()
}