Module cranelift_codegen::isa::x64::encoding::evex

Encodes EVEX instructions. These instructions are those added by the AVX-512 extensions. The EVEX encoding requires a 4-byte prefix:

Byte 0: 0x62 ┌───┬───┬───┬───┬───┬───┬───┬───┐ Byte 1: │ R │ X │ B │ R’│ 0 │ 0 │ m │ m │ ├───┼───┼───┼───┼───┼───┼───┼───┤ Byte 2: │ W │ v │ v │ v │ v │ 1 │ p │ p │ ├───┼───┼───┼───┼───┼───┼───┼───┤ Byte 3: │ z │ L’│ L │ b │ V’│ a │ a │ a │ └───┴───┴───┴───┴───┴───┴───┴───┘

The prefix is then followed by the opcode byte, the ModR/M byte, and other optional suffixes (e.g. SIB byte, displacements, immediates) based on the instruction (see section 2.6, Intel Software Development Manual, volume 2A).

Structs

• EvexInstruction
  Constructs an EVEX-encoded instruction using a builder pattern. This approach makes it visually easier to transform something the manual’s syntax, EVEX.256.66.0F38.W1 1F /r to code: EvexInstruction::new().length(...).prefix(...).map(...).w(true).opcode(0x1F).reg(...).rm(...).
• Register
  Describe the register index to use. This wrapper is a type-safe way to pass around the registers defined in inst/regs.rs.

Enums

• EvexContext
  Defines the EVEX context for the L', L, and b bits (bits 6:4 of EVEX P2 byte). Table 2-36 in section 2.6.10 (Intel Software Development Manual, volume 2A) describes how these bits can be used together for certain classes of instructions; i.e., special care should be taken to ensure that instructions use an applicable correct EvexContext. Table 2-39 contains cases where opcodes can result in an #UD.
• EvexMasking
  Defines the EVEX masking behavior; masking support is described in section 2.6.4 of the Intel Software Development Manual, volume 2A.
• EvexRoundingControl
  The EVEX format allows defining rounding control in the L' and L bits; see EvexContext.
• EvexVectorLength
  The EVEX format allows choosing a vector length in the L' and L bits; see EvexContext.
• RegisterOrAmode