Module cranelift_codegen::isa::x64::args
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Instruction operand sub-components (aka “parts”): definitions and printing.
Structs
- A newtype wrapper around
Reg
. - A newtype wrapper around
RegMem
for general-purpose registers. - A newtype wrapper around
RegMemImm
. - A newtype wrapper around
Imm8Reg
. - A newtype wrapper around
Imm8Reg
. - A newtype wrapper around
Reg
. - A newtype wrapper around
RegMem
for general-purpose registers. - A newtype wrapper around
RegMemImm
.
Enums
- Some basic ALU operations. TODO: maybe add Adc, Sbb.
- Internal type Amode: defined at src/isa/x64/inst.isle line 832.
- These indicate condition code tests. Not all are represented since not all are useful in compiler-generated code.
- Comparison operations.
- What kind of division or remainder instruction this is?
- This defines the ways a value can be extended: either signed- or zero-extension, or none for types that are not extended. Contrast with ExtMode, which defines the widths from and to which values can be extended.
- These indicate ways of extending (widening) a value, using the Intel naming: B(yte) = u8, W(ord) = u16, L(ong)word = u32, Q(uad)word = u64
- Encode the ways that floats can be compared. This is used in float comparisons such as
cmpps
, e.g.; it is distinguished from other float comparisons (e.g.ucomiss
) in that those use EFLAGS whereas FcmpImm is used as an immediate. - An x64 memory fence kind.
- An operand which is either an 8-bit integer immediate or a register.
- An operand’s size in bits.
- An operand which is either an integer Register or a value in Memory. This can denote an 8, 16, 32, 64, or 128 bit value.
- An operand which is either an integer Register, a value in Memory or an Immediate. This can denote an 8, 16, 32 or 64 bit value. For the Immediate form, in the 8- and 16-bit case, only the lower 8 or 16 bits of
simm32
is relevant. In the 64-bit case, the value denoted bysimm32
is its sign-extension out to 64 bits. - Encode the rounding modes used as part of the Rounding Control field. Note, these rounding immediates only consider the rounding control field (i.e. the rounding mode) which only take up the first two bits when encoded. However the rounding immediate which this field helps make up, also includes bits 3 and 4 which define the rounding select and precision mask respectively. These two bits are not defined here and are implictly set to zero when encoded.
- These indicate the form of a scalar shift/rotate: left, signed right, unsigned right.
- Some SSE operations requiring 2 operands r/m and r.
- A Memory Address. These denote a 64-bit value only. Used for usual addressing modes as well as addressing modes used during compilation, when the moving SP offset is not known.
- Unary operations requiring register or memory and register operands.
Traits
- An extension trait for converting
Writable<Reg>
toWritable{Xmm,Gpr}
. - An extenstion trait for converting
Writable{Xmm,Gpr}
toWritable<Reg>
.
Type Definitions
- Optional writable Gpr.
- Optional writable Gpr.
- Writable Gpr.
- Writable Gpr.