andes-riscv 0.1.0

Low level access to Andes' AndeStar V5 RISC-V processors
Documentation
1
2
3
4
5
6
{
  "git": {
    "sha1": "5a03b42ecd5a9321c7c7061d5f114df0722d2f11"
  },
  "path_in_vcs": ""
}