andes-riscv 0.1.0

Low level access to Andes' AndeStar V5 RISC-V processors
Documentation 
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[dependencies.riscv]
version = "0.11.1"

[lib]
name = "andes_riscv"
path = "src/lib.rs"

[package]
authors = ["Andelf <andelf@gmail.com>"]
autobenches = false
autobins = false
autoexamples = false
autolib = false
autotests = false
build = false
categories = ["embedded", "no-std", "hardware-support"]
description = "Low level access to Andes' AndeStar V5 RISC-V processors"
documentation = "https://docs.rs/andes-riscv"
edition = "2021"
homepage = "https://github.com/embedded-drivers/andes-riscv"
keywords = ["andes", "riscv"]
license = "MIT/Apache-2.0"
name = "andes-riscv"
readme = "README.md"
repository = "https://github.com/embedded-drivers/andes-riscv"
version = "0.1.0"

[package.metadata.docs.rs]
default-target = "riscv32imafc-unknown-none-elf"