andes-riscv 0.1.0

Low level access to Andes' AndeStar V5 RISC-V processors
Documentation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
# AndeStar V5 machine mode CSRs and debug mode CSRs
block/CSR:
  description: Machine Mode CSRs and Debug Mode CSRs
  items:
    # Configuration Registers
    - name: micm_cfg
      byte_offset: 0xFC0
      description: Instruction cache/memory configuration
      fieldset: MICM_CFG
    - name: mdcm_cfg
      byte_offset: 0xFC1
      description: Data cache/memory configuration
      fieldset: MDCM_CFG
    - name: mmsc_cfg
      byte_offset: 0xFC2
      description: Miscellaneous configuration
      fieldset: MMSC_CFG
    - name: mmsc_cfg2
      byte_offset: 0xFC3
      description: Miscellaneous configuration (RV32)
      fieldset: MMSC_CFG2
    - name: mvec_cfg
      byte_offset: 0xFC7
      description: Vector processor configuration
      fieldset: MVEC_CFG
    - name: mccache_ctl_base
      byte_offset: 0xFCF
      description: Cluster cache control base address
    - name: mrvarch_cfg
      byte_offset: 0xFCA
      description: RISC-V Architecture
      fieldset: MRVARCH_CFG
    # Crash Debug CSRs
    - name: mcrash_statesave
      byte_offset: 0xFC8
      description: Current state save for crash debugging
      fieldset: MCRASH_STATESAVE
    - name: mstatus_crashsave
      byte_offset: 0xFC9
      description: mstatus state save for crash debugging
    # Memory CSRs
    - name: milmb
      byte_offset: 0x7C0
      description: Instruction local memory base address.
      fieldset: MILMB
    - name: mdlmb
      byte_offset: 0x7C1
      description: Data local memory base address.
      fieldset: MDLMB
    - name: mecc_code
      byte_offset: 0x7C2
      description: ECC code.
      fieldset: MECC_CODE
    - name: mnvec
      byte_offset: 0x7C3
      description: NMI-handler base address.
    - name: mcache_ctl
      byte_offset: 0x7CA
      description: Cache control
      fieldset: MCACHE_CTL
    - name: mcctlbeginaddr
      byte_offset: 0x7CB
      description: CCTL begin address
    - name: mcctlcommand
      byte_offset: 0x7CC
      description: CCTL command
    - name: mcctldata
      byte_offset: 0x7CD
      description: CCTL data
    - name: mppib
      byte_offset: 0x7F0
      description: Private peripheral interface base address
      fieldset: MPPIB
    - name: mfiob
      byte_offset: 0x7F1
      description: Fast IO interface base address
      fieldset: MFIOB
    # Hardware Stack Protection & Recording
    - name: mhsp_ctl
      byte_offset: 0x7C6
      description: Hardware stack protection control
      fieldset: MHSP_CTL
    - name: msp_bound
      byte_offset: 0x7C7
      description: SP bound register
    - name: msp_base
      byte_offset: 0x7C8
      description: SP base register
    # Trap related CSR
    - name: mxstatus
      byte_offset: 0x7C4
      description: Additional machine mode status
      fieldset: MXSTATUS
    - name: mdcause
      byte_offset: 0x7C9
      description: Detailed exception cause
      fieldset: MDCAUSE
    - name: mslideleg
      byte_offset: 0x7D5
      description: Supervisor local interrupt delegation
      fieldset: MSLIDELEG
    - name: msavestatus
      byte_offset: 0x7D6
      description: Status save register (level 1 & level 2)
      fieldset: MSAVESTATUS
    - name: msaveepc1
      byte_offset: 0x7D7
      description: EPC save register (level 1)
    - name: msavecause1
      byte_offset: 0x7D8
      description: Exception cause save register (level 1)
    - name: msaveepc2
      byte_offset: 0x7D9
      description: EPC save register (level 2)
    - name: msavecause2
      byte_offset: 0x7DA
      description: Exception cause save register (level 2)
    - name: msavedcause1
      byte_offset: 0x7DB
      description: Detailed exception cause save (level 1)
    - name: msavedcause2
      byte_offset: 0x7DC
      description: Detailed exception cause save (level 2)
    # Control CSRs
    - name: mpft_ctl
      byte_offset: 0x7C5
      description: Performance throttling control
      fieldset: MPFT_CTL
    - name: mmisc_ctl
      byte_offset: 0x7D0
      description: Miscellaneous control
      fieldset: MMISC_CTL
    - name: mclk_ctl
      byte_offset: 0x7DF
      description: Clock control
    # Counter related CSRs
    - name: mcounterwen
      byte_offset: 0x7CE
      description: Counter write enable
      fieldset: MCOUNTER_COMMON
    - name: mcounterinten
      byte_offset: 0x7CF
      description: Counter overflow interrupt enable
      fieldset: MCOUNTER_COMMON
    - name: mcountermask_m
      byte_offset: 0x7D1
      description: Counter not counting in M-mode
      fieldset: MCOUNTER_COMMON
    - name: mcountermask_s
      byte_offset: 0x7D2
      description: Counter not counting in S-mode
      fieldset: MCOUNTER_COMMON
    - name: mcountermask_u
      byte_offset: 0x7D3
      description: Counter not counting in U-mode
      fieldset: MCOUNTER_COMMON
    - name: mcounterovf
      byte_offset: 0x7D4
      description: Counter overflow status
      fieldset: MCOUNTER_COMMON
    # Enhanced CLIC CSRs
    - name: mirq_entry
      byte_offset: 0x7EC
      description: Interrupt common entry point
      fieldset: MIRQ_ENTRY
    - name: mintsel_jal
      byte_offset: 0x7ED
      description: Select interrupt and call ISR
    - name: pushmcause
      byte_offset: 0x7EE
      description: Store mcause to stack
    - name: pushmepc
      byte_offset: 0x7EF
      description: Store mepc to stack
    - name: pushmxstatus
      byte_offset: 0x7EB
      description: Store mxstatus to stack
    # Physical Memory Attribute CSRs
    - name: pmacfg0
      byte_offset: 0xBC0
      description: PMA configuration
      fieldset: PMACFG
    - name: pmacfg1
      byte_offset: 0xBC0
      description: PMA configuration
      fieldset: PMACFG
    - name: pmacfg2
      byte_offset: 0xBC0
      description: PMA configuration
      fieldset: PMACFG
    - name: pmacfg3
      byte_offset: 0xBC0
      description: PMA configuration
      fieldset: PMACFG
    # pmaaddr0 to pmaaddr15
    - name: pmaaddr0
      byte_offset: 0xBD0
      description: PMA address
    - name: pmaaddr1
      byte_offset: 0xBD1
      description: PMA address
    - name: pmaaddr2
      byte_offset: 0xBD2
      description: PMA address
    - name: pmaaddr3
      byte_offset: 0xBD3
      description: PMA address
    - name: pmaaddr4
      byte_offset: 0xBD4
      description: PMA address
    - name: pmaaddr5
      byte_offset: 0xBD5
      description: PMA address
    - name: pmaaddr6
      byte_offset: 0xBD6
      description: PMA address
    - name: pmaaddr7
      byte_offset: 0xBD7
      description: PMA address
    - name: pmaaddr8
      byte_offset: 0xBD8
      description: PMA address
    - name: pmaaddr9
      byte_offset: 0xBD9
      description: PMA address
    - name: pmaaddr10
      byte_offset: 0xBDA
      description: PMA address
    - name: pmaaddr11
      byte_offset: 0xBDB
      description: PMA address
    - name: pmaaddr12
      byte_offset: 0xBDC
      description: PMA address
    - name: pmaaddr13
      byte_offset: 0xBDD
      description: PMA address
    - name: pmaaddr14
      byte_offset: 0xBDE
      description: PMA address
    - name: pmaaddr15
      byte_offset: 0xBDF
      description: PMA address

    # AndeStar V5 debug mode CSRs
    - name: dexc2dbg
      byte_offset: 0x7E0
      description: Enable exception to enter Halt Mode.
      fieldset: DEXC2DBG
    - name: ddcause
      byte_offset: 0x7E1
      description: Detailed exception type information when an exception enters Halt Mode.
      fieldset: DDCAUSE
# - MARK: fieldsets
fieldset/MICM_CFG:
  description: Instruction Cache/Memory Configuration Register
  fields:
    - name: ISET
      description:
      bit_offset: 0
      bit_size: 3
    - name: IWAY
      description:
      bit_offset: 3
      bit_size: 3
    - name: ISZ
      description:
      bit_offset: 6
      bit_size: 3
    - name: ILCK
      description:
      bit_offset: 9
      bit_size: 1
    - name: IC_ECC
      description:
      bit_offset: 10
      bit_size: 2
    - name: ILMB
      description:
      bit_offset: 12
      bit_size: 3
    - name: ILMSZ
      description:
      bit_offset: 15
      bit_size: 5
    - name: ULM_2BANK
      description:
      bit_offset: 20
      bit_size: 1
    - name: ILM_ECC
      description:
      bit_offset: 21
      bit_size: 2
    - name: ILM_XONLY
      description:
      bit_offset: 23
      bit_size: 1
    - name: SETH
      description:
      bit_offset: 24
      bit_size: 1
    - name: IC_REPL
      description:
      bit_offset: 25
      bit_size: 2
fieldset/MDCM_CFG:
  description: Data Cache/Memory Configuration Register
  fields:
    - name: DSET
      description:
      bit_offset: 0
      bit_size: 3
    - name: DWAY
      description:
      bit_offset: 3
      bit_size: 3
    - name: DSZ
      description:
      bit_offset: 6
      bit_size: 3
    - name: DLCK
      description:
      bit_offset: 9
      bit_size: 1
    - name: DC_ECC
      description:
      bit_offset: 10
      bit_size: 2
    - name: DLMB
      description:
      bit_offset: 12
      bit_size: 3
    - name: DLMSZ
      description:
      bit_offset: 15
      bit_size: 5
    - name: ULM_2BANK
      description:
      bit_offset: 20
      bit_size: 1
    - name: DLM_ECC
      description:
      bit_offset: 21
      bit_size: 2
    - name: SETH
      description:
      bit_offset: 24
      bit_size: 1
    - name: DC_REPL
      description:
      bit_offset: 25
      bit_size: 2
fieldset/MMSC_CFG:
  description: Misc. Configuration Register
  fields:
    - name: ECC
      description:
      bit_offset: 0
      bit_size: 1
    - name: TLB_ECC
      description:
      bit_offset: 1
      bit_size: 2
    - name: ECD
      description:
      bit_offset: 3
      bit_size: 1
    - name: PFT
      description:
      bit_offset: 4
      bit_size: 1
    - name: HSP
      description:
      bit_offset: 5
      bit_size: 1
    - name: ACE
      description:
      bit_offset: 6
      bit_size: 1
    - name: ADDPMC
      description:
      bit_offset: 7
      bit_size: 5
    - name: VPLIC
      description:
      bit_offset: 12
      bit_size: 1
    - name: EV5PE
      description:
      bit_offset: 13
      bit_size: 1
    - name: LMSLVP
      description:
      bit_offset: 14
      bit_size: 1
    - name: PMNDS
      description:
      bit_offset: 15
      bit_size: 1
    - name: CCTLCSR
      description:
      bit_offset: 16
      bit_size: 1
    - name: EFHW
      description:
      bit_offset: 17
      bit_size: 1
    - name: VCCTL
      description:
      bit_offset: 18
      bit_size: 2
    - name: EXCSLVL
      description:
      bit_offset: 20
      bit_size: 2
    - name: NOPMC
      description:
      bit_offset: 22
      bit_size: 1
    - name: SPE_AFT
      description:
      bit_offset: 23
      bit_size: 1
    - name: ESLEEP
      description:
      bit_offset: 24
      bit_size: 1
    - name: PPI
      description:
      bit_offset: 25
      bit_size: 1
    - name: FIO
      description:
      bit_offset: 26
      bit_size: 1
    - name: CLIC
      description:
      bit_offset: 27
      bit_size: 1
    - name: ECLIC
      description:
      bit_offset: 28
      bit_size: 1
    - name: EDSP
      description:
      bit_offset: 29
      bit_size: 1
    - name: PPMA
      description:
      bit_offset: 30
      bit_size: 1
    - name: MSC_EXT
      description:
      bit_offset: 31
      bit_size: 1
fieldset/MMSC_CFG2:
  description: Misc. Configuration 2 Register
  fields:
    - name: BF16CVT
      description:
      bit_offset: 0
      bit_size: 1
    - name: ZFH
      description:
      bit_offset: 1
      bit_size: 1
    - name: VL4
      description:
      bit_offset: 2
      bit_size: 1
    - name: CRASHSAVE
      description:
      bit_offset: 3
      bit_size: 1
    - name: VECCFG
      description:
      bit_offset: 4
      bit_size: 1
    - name: FINV
      description:
      bit_offset: 5
      bit_size: 1
    - name: PP16
      description:
      bit_offset: 6
      bit_size: 1
    - name: VSIH
      description:
      bit_offset: 8
      bit_size: 1
    - name: ECDV
      description:
      bit_offset: 9
      bit_size: 2
    - name: VDOT
      description:
      bit_offset: 11
      bit_size: 1
    - name: VPFH
      description:
      bit_offset: 12
      bit_size: 1
    - name: CCACHEMP_CFG
      description:
      bit_offset: 13
      bit_size: 1
    - name: CCACHE
      description:
      bit_offset: 14
      bit_size: 1
    - name: IO_COHP
      description:
      bit_offset: 15
      bit_size: 1
    - name: CORE_PCLUS
      description:
      bit_offset: 16
      bit_size: 4
    - name: RVARCH
      description:
      bit_offset: 20
      bit_size: 1
fieldset/MCRASH_STATESAVE:
  description: Machine Crash State Save
  fields:
    - name: MIE
      description:
      bit_offset: 0
      bit_size: 1
    - name: CP
      description:
      bit_offset: 1
      bit_size: 2
    - name: PPFT_EN
      description:
      bit_offset: 3
      bit_size: 1
    - name: PIME
      description:
      bit_offset: 4
      bit_size: 1
    - name: PDME
      description:
      bit_offset: 5
      bit_size: 1
    - name: PTYP
      description:
      bit_offset: 6
      bit_size: 2
fieldset/MVEC_CFG:
  description: Vector Configuration Register
  fields:
    - name: MINOR
      description:
      bit_offset: 0
      bit_size: 4
    - name: MAJOR
      description:
      bit_offset: 4
      bit_size: 4
    - name: DW
      description:
      bit_offset: 8
      bit_size: 3
    - name: MW
      description:
      bit_offset: 11
      bit_size: 3
    - name: MISEW
      description:
      bit_offset: 14
      bit_size: 2
    - name: MFSEW
      description:
      bit_offset: 16
      bit_size: 2
fieldset/MRVARCH_CFG:
  description: RISC-V Architecture Configuration Register
  fields:
    - name: Zba
      description:
      bit_offset: 0
      bit_size: 1
    - name: Zbb
      description:
      bit_offset: 1
      bit_size: 1
    - name: Zbc
      description:
      bit_offset: 2
      bit_size: 1
    - name: Zbs
      description:
      bit_offset: 3
      bit_size: 1
    - name: Smepmp
      description:
      bit_offset: 4
      bit_size: 1
    - name: Svinval
      description:
      bit_offset: 5
      bit_size: 1
    - name: Smstateen
      description:
      bit_offset: 6
      bit_size: 1
    - name: Sscofmpf
      description:
      bit_offset: 7
      bit_size: 1
    - name: Sstc
      description:
      bit_offset: 8
      bit_size: 1
    - name: Zicbom
      description:
      bit_offset: 9
      bit_size: 1
    - name: Zicbop
      description:
      bit_offset: 10
      bit_size: 1
    - name: Zicboz
      description:
      bit_offset: 11
      bit_size: 1
    - name: Zbk
      description:
      bit_offset: 12
      bit_size: 1
    - name: Zkn
      description:
      bit_offset: 13
      bit_size: 1
    - name: Zks
      description:
      bit_offset: 14
      bit_size: 1
    - name: Zkt
      description:
      bit_offset: 15
      bit_size: 1
    - name: Zkr
      description:
      bit_offset: 16
      bit_size: 1
    - name: SM_VERION
      description:
      bit_offset: 17
      bit_size: 3
    - name: SS_VERSION
      description:
      bit_offset: 20
      bit_size: 3
    - name: Svpbmt
      description:
      bit_offset: 23
      bit_size: 1
    - name: Svnapot
      description:
      bit_offset: 24
      bit_size: 1
    - name: Zihintpause
      description:
      bit_offset: 25
      bit_size: 1
fieldset/MILMB:
  description: ILM (Instruction Local Memory) Base Register
  fields:
    - name: IEN
      description: ILM Enable
      bit_offset: 0
      bit_size: 1
    - name: ECCEN
      description: ECC Enable
      bit_offset: 1
      bit_size: 2
    - name: RWECC
      description: Read/Write ECC
      bit_offset: 3
      bit_size: 1
    - name: IBPA
      description: Base Physical Address (IBPA)
      bit_offset: 10
      bit_size: 22 # NOTE: 32-bit
fieldset/MDLMB:
  description: DLM (Data Local Memory) Base Register
  fields:
    - name: DEN
      description: DLM Enable
      bit_offset: 0
      bit_size: 1
    - name: ECCEN
      description: ECC Enable
      bit_offset: 1
      bit_size: 2
    - name: RWECC
      description: Read/Write ECC
      bit_offset: 3
      bit_size: 1
    - name: Reserved
      description: Reserved
      bit_offset: 4
      bit_size: 6
    - name: DBPA
      description: Base Physical Address (DBPA)
      bit_offset: 10
      bit_size: 22 # NOTE: 32-bit
fieldset/MECC_CODE:
  description: ECC Code Register
  fields:
    - name: Code
      description: ECC Code
      bit_offset: 0
      bit_size: 7 # 8 for RV64
    - name: C
      description: Correctable Error Flag
      bit_offset: 16
      bit_size: 1
    - name: P
      description: Parity Error Flag
      bit_offset: 17
      bit_size: 1
    - name: RAMID
      description: RAM Identifier
      bit_offset: 18
      bit_size: 4
    - name: INSN
      description: Instruction Error Flag
      bit_offset: 22
      bit_size: 1
    - name: SYNDR
      description: Syndrome
      bit_offset: 23
      bit_size: 1
fieldset/MPFT_CTL:
  description: Performance Throttling Control Register
  fields:
    - name: T_LEVEL
      description: Throttling Level
      bit_offset: 4
      bit_size: 4
    - name: FAST_INT
      description: Fast Interrupt
      bit_offset: 8
      bit_size: 1
fieldset/MCACHE_CTL:
  description: Cache Control Register
  fields:
    - name: IC_EN
      description: Instruction Cache Enable
      bit_offset: 0
      bit_size: 1
    - name: DC_EN
      description: Data Cache Enable
      bit_offset: 1
      bit_size: 1
    - name: IC_ECCEN
      description: Instruction Cache ECC Enable
      bit_offset: 2
      bit_size: 2
    - name: DC_ECCEN
      description: Data Cache ECC Enable
      bit_offset: 4
      bit_size: 2
    - name: IC_RWECC
      description: Instruction Cache Read/Write ECC
      bit_offset: 6
      bit_size: 1
    - name: DC_RWECC
      description: Data Cache Read/Write ECC
      bit_offset: 7
      bit_size: 1
    - name: CCTL_SUEN
      description: Cache Control SU Enable
      bit_offset: 8
      bit_size: 1
    - name: IPREF_EN
      description: Instruction Prefetch Enable
      bit_offset: 9
      bit_size: 1
    - name: DPREF_EN
      description: Data Prefetch Enable
      bit_offset: 10
      bit_size: 1
    - name: IC_1ST_WD
      description: Instruction Cache 1st Way Disable
      bit_offset: 11
      bit_size: 1
    - name: DC_1ST_WD
      description: Data Cache 1st Way Disable
      bit_offset: 12
      bit_size: 1
    - name: DC_WARND
      description: Data Cache Write-Around
      bit_offset: 13
      bit_size: 2
    - name: L2C_WARND
      description: L2 Cache Write-Around
      bit_offset: 15
      bit_size: 2
    - name: TLB_ECCEN
      description: TLB ECC Enable
      bit_offset: 17
      bit_size: 2
    - name: DC_COHEN
      description: Data Cache Coherence Enable
      bit_offset: 19
      bit_size: 1
    - name: DC_COHSTA
      description: Data Cache Coherence State
      bit_offset: 20
      bit_size: 1
    - name: DPREF_MODE
      description: Data Prefetch Mode
      bit_offset: 21
      bit_size: 2
fieldset/MMISC_CTL:
  description: Machine Miscellaneous Control Register
  fields:
    - name: ACE
      description: Andes Custom Extension (ACE) enable
      bit_offset: 0
      bit_size: 1
    - name: VEC_PLIC
      description: Vectored external PLIC interrupt enable
      bit_offset: 1
      bit_size: 1
    - name: RVCOMPM
      description: RV compatibility mode enable bit
      bit_offset: 2
      bit_size: 1
    - name: BRPE
      description:
      bit_offset: 3
      bit_size: 1
    - name: ACES
      description:
      bit_offset: 4
      bit_size: 2
    - name: MSA_UNA
      description:
      bit_offset: 6
      bit_size: 1
    - name: NBLD_EN
      description:
      bit_offset: 8
      bit_size: 1
    - name: NEWNMI
      description:
      bit_offset: 9
      bit_size: 1
    - name: VCGL1_EN
      description:
      bit_offset: 10
      bit_size: 1
    - name: VCGL2_EN
      description:
      bit_offset: 11
      bit_size: 1
    - name: VCGL3_EN
      description:
      bit_offset: 12
      bit_size: 1
    - name: LDX0NXP
      description: “Load to x0” exception generation control bit
      bit_offset: 13
      bit_size: 1
fieldset/MPPIB:
  description: PPI (Private Peripheral Interface) Base Register
  fields:
    - name: EN
      description: Private Peripheral Interface enable bit
      bit_offset: 0
      bit_size: 1
    - name: SIZE
      description: Indicates the power-of-2 size of the PPI region
      bit_offset: 1
      bit_size: 5
    - name: BPA
      description: Base Physical Address
      bit_offset: 10
      bit_size: 22 # NOTE: 32-bit
fieldset/MFIOB:
  description: FIO (Fast IO Interface) Base Register
  fields:
    - name: EN
      description:
      bit_offset: 0
      bit_size: 1
    - name: SIZE
      description:
      bit_offset: 1
      bit_size: 5
    - name: BPA
      description: Base Physical Address
      bit_offset: 10
      bit_size: 22 # NOTE: 32-bit
fieldset/MXSTATUS:
  description: Machine Extended Status Register
  fields:
    - name: PFT_EN
      description:
      bit_offset: 0
      bit_size: 1
    - name: PPFT_EN
      description:
      bit_offset: 1
      bit_size: 1
    - name: IME
      description:
      bit_offset: 2
      bit_size: 1
    - name: PIME
      description:
      bit_offset: 3
      bit_size: 1
    - name: DME
      description:
      bit_offset: 4
      bit_size: 1
    - name: PDME
      description:
      bit_offset: 5
      bit_size: 1
    - name: TYP
      description:
      bit_offset: 6
      bit_size: 2
    - name: PTYP
      description:
      bit_offset: 8
      bit_size: 2
fieldset/MDCAUSE:
  description: Machine Detailed Trap Cause Register (for imprecise exception/interrupt)
  fields:
    - name: mdcause
      description:
      bit_offset: 0
      bit_size: 5
    - name: PM
      description:
      bit_offset: 5
      bit_size: 2
fieldset/MSLIDELEG:
  description: Machine Supervisor Local Interrupt Delegation Register
  fields:
    - name: IMECCI
      description:
      bit_offset: 16
      bit_size: 1
    - name: BWEI
      description:
      bit_offset: 17
      bit_size: 1
    - name: PMOVI
      description:
      bit_offset: 18
      bit_size: 1
    - name: IMECCDMR
      description:
      bit_offset: 19
      bit_size: 1
    - name: ACEERR
      description:
      bit_offset: 24
      bit_size: 1
fieldset/MSAVESTATUS:
  description: Machine Status Save Register
  fields:
    - name: MPIE
      description:
      bit_offset: 0
      bit_size: 1
    - name: MPP
      description:
      bit_offset: 1
      bit_size: 2
    - name: PPFT_EN
      description:
      bit_offset: 3
      bit_size: 1
    - name: PIME
      description:
      bit_offset: 4
      bit_size: 1
    - name: PDME
      description:
      bit_offset: 5
      bit_size: 1
    - name: PTYP
      description:
      bit_offset: 6
      bit_size: 2
fieldset/MHSP_CTL:
  description: Machine Hardware Stack Protection Control Register
  fields:
    - name: OVF_EN
      description:
      bit_offset: 0
      bit_size: 1
    - name: UDF_EN
      description:
      bit_offset: 1
      bit_size: 1
    - name: SCHM
      description:
      bit_offset: 2
      bit_size: 1
    - name: U
      description:
      bit_offset: 3
      bit_size: 1
    - name: S
      description:
      bit_offset: 4
      bit_size: 1
    - name: M
      description:
      bit_offset: 5
      bit_size: 1
fieldset/MIRQ_ENTRY:
  description: Machine Interrupt Common Entry Address Register
  fields:
    - name: EN
      description: Enable
      bit_offset: 0
      bit_size: 1
    - name: ICEA
      description: Interrupt Common Entry Address
      bit_offset: 1
      bit_size: 31
fieldset/DEXC2DBG:
  description: Exception Redirection Register
  fields:
    - name: IAM
      description:
      bit_offset: 0
      bit_size: 1
    - name: IAF
      description:
      bit_offset: 1
      bit_size: 1
    - name: II
      description:
      bit_offset: 2
      bit_size: 1
    - name: NMI
      description:
      bit_offset: 3
      bit_size: 1
    - name: LAM
      description:
      bit_offset: 4
      bit_size: 1
    - name: LAF
      description:
      bit_offset: 5
      bit_size: 1
    - name: SAM
      description:
      bit_offset: 6
      bit_size: 1
    - name: SAF
      description:
      bit_offset: 7
      bit_size: 1
    - name: UEC
      description:
      bit_offset: 8
      bit_size: 1
    - name: SEC
      description:
      bit_offset: 9
      bit_size: 1
    - name: HEC
      description:
      bit_offset: 10
      bit_size: 1
    - name: MEC
      description:
      bit_offset: 11
      bit_size: 1
    - name: HSP
      description:
      bit_offset: 12
      bit_size: 1
    - name: ACE
      description:
      bit_offset: 13
      bit_size: 1
    - name: SLPECC
      description:
      bit_offset: 14
      bit_size: 1
    - name: BWE
      description:
      bit_offset: 15
      bit_size: 1
    - name: IPF
      description:
      bit_offset: 16
      bit_size: 1
    - name: LPF
      description:
      bit_offset: 17
      bit_size: 1
    - name: SPF
      description:
      bit_offset: 18
      bit_size: 1
    - name: PMOV
      description:
      bit_offset: 19
      bit_size: 1
fieldset/DDCAUSE:
  description: Debug Detailed Cause Register
  fields:
    - name: MAINTYPE
      description: Indicates the main types of a Debug Mode entrance. Its definition is listed below.
      bit_offset: 0
      bit_size: 8
    - name: SUBTYPE
      description: Indicates the subtypes of a main type. Its definition is listed below. A main type may not have a subtype definition.
      bit_offset: 8
      bit_size: 8
fieldset/MCOUNTER_COMMON:
  description: Machine Counter Fields
  fields:
    - name: CY
      description: Cycle counter
      bit_offset: 0
      bit_size: 1
    - name: IR
      description: Instruction retired counter
      bit_offset: 2
      bit_size: 1
    - name: HPM
      description: Hardware performance monitor 3 to 31
      bit_offset: 3
      bit_size: 1
      array:
        len: 29
        stride: 1
        start_index: 3 # TODO, support this
fieldset/PMACFG:
  description: PMA Configuration Register 0
  fields:
    - name: ETYP
      description: Event Type
      bit_offset: 0
      bit_size: 2
      array:
        len: 4
        stride: 4
    - name: MTYP
      description: Memory Type
      bit_offset: 2
      bit_size: 4
      array:
        len: 4
        stride: 4
    - name: NAMO
      description: Naturally Aligned Memory Operation
      bit_offset: 6
      bit_size: 1
      array:
        len: 4
        stride: 4