embassy_stm32/dac/
tsel.rs

1#![allow(missing_docs)]
2
3/// Trigger selection for STM32F0.
4#[cfg(stm32f0)]
5#[derive(Debug, Copy, Clone, Eq, PartialEq)]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7pub enum TriggerSel {
8    Tim6 = 0,
9    Tim3 = 1,
10    Tim7 = 2,
11    Tim15 = 3,
12    Tim2 = 4,
13    Exti9 = 6,
14    Software = 7,
15}
16
17/// Trigger selection for STM32F1.
18#[cfg(stm32f1)]
19#[derive(Debug, Copy, Clone, Eq, PartialEq)]
20#[cfg_attr(feature = "defmt", derive(defmt::Format))]
21pub enum TriggerSel {
22    Tim6 = 0,
23    #[cfg(any(stm32f100, stm32f105, stm32f107))]
24    Tim3 = 1,
25    #[cfg(any(stm32f101, stm32f103))]
26    Tim8 = 1,
27    Tim7 = 2,
28    #[cfg(any(stm32f101, stm32f103, stm32f105, stm32f107))]
29    Tim5 = 3,
30    #[cfg(all(stm32f100, any(flashsize_4, flashsize_6, flashsize_8, flashsize_b)))]
31    Tim15 = 3,
32    #[cfg(all(stm32f100, any(flashsize_c, flashsize_d, flashsize_e)))]
33    /// Can be remapped to TIM15 with MISC_REMAP in AFIO_MAPR2.
34    Tim5Or15 = 3,
35    Tim2 = 4,
36    Tim4 = 5,
37    Exti9 = 6,
38    Software = 7,
39}
40
41/// Trigger selection for STM32F2/F4/F7/L4, except F410 or L4+.
42#[cfg(all(any(stm32f2, stm32f4, stm32f7, stm32l4_nonplus), not(stm32f410)))]
43#[derive(Debug, Copy, Clone, Eq, PartialEq)]
44#[cfg_attr(feature = "defmt", derive(defmt::Format))]
45pub enum TriggerSel {
46    Tim6 = 0,
47    Tim8 = 1,
48    #[cfg(not(any(stm32l45x, stm32l46x)))]
49    Tim7 = 2,
50    Tim5 = 3,
51    Tim2 = 4,
52    Tim4 = 5,
53    Exti9 = 6,
54    Software = 7,
55}
56
57/// Trigger selection for STM32F410.
58#[cfg(stm32f410)]
59#[derive(Debug, Copy, Clone, Eq, PartialEq)]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61pub enum TriggerSel {
62    Tim5 = 3,
63    Exti9 = 6,
64    Software = 7,
65}
66
67/// Trigger selection for STM32F301/2 and 318.
68#[cfg(any(stm32f301, stm32f302, stm32f318))]
69#[derive(Debug, Copy, Clone, Eq, PartialEq)]
70#[cfg_attr(feature = "defmt", derive(defmt::Format))]
71pub enum TriggerSel {
72    Tim6 = 0,
73    #[cfg(stm32f302)]
74    /// Requires DAC_TRIG_RMP set in SYSCFG_CFGR1.
75    Tim3 = 1,
76    Tim15 = 3,
77    Tim2 = 4,
78    #[cfg(all(stm32f302, any(flashsize_6, flashsize_8)))]
79    Tim4 = 5,
80    Exti9 = 6,
81    Software = 7,
82}
83
84/// Trigger selection for STM32F303/3x8 (excluding 318 which is like 301, and 378 which is 37x).
85#[cfg(any(stm32f303, stm32f328, stm32f358, stm32f398))]
86#[derive(Debug, Copy, Clone, Eq, PartialEq)]
87#[cfg_attr(feature = "defmt", derive(defmt::Format))]
88pub enum TriggerSel {
89    Tim6 = 0,
90    /// * DAC1: defaults to TIM8 but can be remapped to TIM3 with DAC_TRIG_RMP in SYSCFG_CFGR1
91    /// * DAC2: always TIM3
92    Tim8Or3 = 1,
93    Tim7 = 2,
94    Tim15 = 3,
95    Tim2 = 4,
96    Tim4 = 5,
97    Exti9 = 6,
98    Software = 7,
99}
100
101/// Trigger selection for STM32F37x.
102#[cfg(any(stm32f373, stm32f378))]
103#[derive(Debug, Copy, Clone, Eq, PartialEq)]
104#[cfg_attr(feature = "defmt", derive(defmt::Format))]
105pub enum TriggerSel {
106    Tim6 = 0,
107    Tim3 = 1,
108    Tim7 = 2,
109    /// TIM5 on DAC1, TIM18 on DAC2
110    Dac1Tim5Dac2Tim18 = 3,
111    Tim2 = 4,
112    Tim4 = 5,
113    Exti9 = 6,
114    Software = 7,
115}
116
117/// Trigger selection for STM32F334.
118#[cfg(stm32f334)]
119#[derive(Debug, Copy, Clone, Eq, PartialEq)]
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121pub enum TriggerSel {
122    Tim6 = 0,
123    /// Requires DAC_TRIG_RMP set in SYSCFG_CFGR1.
124    Tim3 = 1,
125    Tim7 = 2,
126    /// Can be remapped to HRTIM_DACTRG1 using DAC1_TRIG3_RMP in SYSCFG_CFGR3.
127    Tim15OrHrtimDacTrg1 = 3,
128    Tim2 = 4,
129    /// Requires DAC_TRIG5_RMP set in SYSCFG_CFGR3.
130    HrtimDacTrg2 = 5,
131}
132
133/// Trigger selection for STM32L0.
134#[cfg(stm32l0)]
135#[derive(Debug, Copy, Clone, Eq, PartialEq)]
136#[cfg_attr(feature = "defmt", derive(defmt::Format))]
137pub enum TriggerSel {
138    Tim6 = 0,
139    Tim3 = 1,
140    Tim3Ch3 = 2,
141    Tim21 = 3,
142    Tim2 = 4,
143    Tim7 = 5,
144    Exti9 = 6,
145    Software = 7,
146}
147
148/// Trigger selection for STM32L1.
149#[cfg(stm32l1)]
150#[derive(Debug, Copy, Clone, Eq, PartialEq)]
151#[cfg_attr(feature = "defmt", derive(defmt::Format))]
152pub enum TriggerSel {
153    Tim6 = 0,
154    Tim7 = 2,
155    Tim9 = 3,
156    Tim2 = 4,
157    Tim4 = 5,
158    Exti9 = 6,
159    Software = 7,
160}
161
162/// Trigger selection for L4+, L5, U5, H7.
163#[cfg(any(stm32l4_plus, stm32l5, stm32u5, stm32h7))]
164#[derive(Debug, Copy, Clone, Eq, PartialEq)]
165#[cfg_attr(feature = "defmt", derive(defmt::Format))]
166pub enum TriggerSel {
167    Software = 0,
168    Tim1 = 1,
169    Tim2 = 2,
170    Tim4 = 3,
171    Tim5 = 4,
172    Tim6 = 5,
173    Tim7 = 6,
174    Tim8 = 7,
175    Tim15 = 8,
176    #[cfg(all(stm32h7, hrtim))]
177    Hrtim1DacTrg1 = 9,
178    #[cfg(all(stm32h7, hrtim))]
179    Hrtim1DacTrg2 = 10,
180    Lptim1 = 11,
181    #[cfg(not(stm32u5))]
182    Lptim2 = 12,
183    #[cfg(stm32u5)]
184    Lptim3 = 12,
185    Exti9 = 13,
186    #[cfg(any(stm32h7ax, stm32h7bx))]
187    /// RM0455 suggests this might be LPTIM2 on DAC1 and LPTIM3 on DAC2,
188    /// but it's probably wrong. Please let us know if you find out.
189    Lptim3 = 14,
190    #[cfg(any(stm32h72x, stm32h73x))]
191    Tim23 = 14,
192    #[cfg(any(stm32h72x, stm32h73x))]
193    Tim24 = 15,
194}
195
196/// Trigger selection for H5.
197#[cfg(stm32h5)]
198#[derive(Debug, Copy, Clone, Eq, PartialEq)]
199#[cfg_attr(feature = "defmt", derive(defmt::Format))]
200pub enum TriggerSel {
201    Software = 0,
202    Tim1 = 1,
203    Tim2 = 2,
204    #[cfg(any(stm32h56x, stm32h57x))]
205    Tim4 = 3,
206    #[cfg(stm32h503)]
207    Tim3 = 3,
208    #[cfg(any(stm32h56x, stm32h57x))]
209    Tim5 = 4,
210    Tim6 = 5,
211    Tim7 = 6,
212    #[cfg(any(stm32h56x, stm32h57x))]
213    Tim8 = 7,
214    #[cfg(any(stm32h56x, stm32h57x))]
215    Tim15 = 8,
216    Lptim1 = 11,
217    Lptim2 = 12,
218    Exti9 = 13,
219}
220
221/// Trigger selection for G0.
222#[cfg(stm32g0)]
223#[derive(Debug, Copy, Clone, Eq, PartialEq)]
224#[cfg_attr(feature = "defmt", derive(defmt::Format))]
225pub enum TriggerSel {
226    Software = 0,
227    Tim1 = 1,
228    Tim2 = 2,
229    Tim3 = 3,
230    Tim6 = 5,
231    Tim7 = 6,
232    Tim15 = 8,
233    Lptim1 = 11,
234    Lptim2 = 12,
235    Exti9 = 13,
236}
237
238/// Trigger selection for U0.
239#[cfg(stm32u0)]
240#[derive(Debug, Copy, Clone, Eq, PartialEq)]
241#[cfg_attr(feature = "defmt", derive(defmt::Format))]
242pub enum TriggerSel {
243    Software = 0,
244    Tim1 = 1,
245    Tim2 = 2,
246    Tim3 = 3,
247    Tim6 = 5,
248    Tim7 = 6,
249    Tim15 = 8,
250    Lptim1 = 11,
251    Lptim2 = 12,
252    Exti9 = 14,
253}
254
255/// Trigger selection for G4.
256#[cfg(stm32g4)]
257#[derive(Debug, Copy, Clone, Eq, PartialEq)]
258#[cfg_attr(feature = "defmt", derive(defmt::Format))]
259pub enum TriggerSel {
260    Software = 0,
261    /// * DAC1, DAC2, DAC4: TIM8
262    /// * DAC3: TIM1
263    Dac124Tim8Dac3Tim1 = 1,
264    Tim7 = 2,
265    Tim15 = 3,
266    Tim2 = 4,
267    Tim4 = 5,
268    Exti9 = 6,
269    Tim6 = 7,
270    Tim3 = 8,
271    HrtimDacRstTrg1 = 9,
272    HrtimDacRstTrg2 = 10,
273    HrtimDacRstTrg3 = 11,
274    HrtimDacRstTrg4 = 12,
275    HrtimDacRstTrg5 = 13,
276    HrtimDacRstTrg6 = 14,
277    /// * DAC1, DAC4: HRTIM_DAC_TRG1
278    /// * DAC2: HRTIM_DAC_TRG2
279    /// * DAC3: HRTIM_DAC_TRG3
280    HrtimDacTrg123 = 15,
281}
282
283/// Trigger selection for WL.
284#[cfg(stm32wl)]
285#[derive(Debug, Copy, Clone, Eq, PartialEq)]
286#[cfg_attr(feature = "defmt", derive(defmt::Format))]
287pub enum TriggerSel {
288    Software = 0,
289    Tim1 = 1,
290    Tim2 = 2,
291    Lptim1 = 11,
292    Lptim2 = 12,
293    Lptim3 = 13,
294    Exti9 = 14,
295}
296
297impl TriggerSel {
298    pub fn tsel(&self) -> u8 {
299        *self as u8
300    }
301}
embassy_stm32/dac/tsel.rs

embassy_stm32/dac/
tsel.rs
