Module moore_svlog::port_list [−][src]
Expand description
A list of ports on a node, with ANSI/non-ANSI styles resolved.
This module implements the port analysis required to determine if a node uses an ANSI or non-ANSI port list, and to match up ports with other bits and pieces in the node body. It produces separate, clean-cut internal and external views of the port list.
More concretely, it does the following:
- Detect ANSI/non-ANSI style
- Fill in implicit port details (defaults and carried-over from previous)
- Combine port declarations in the node body with var/net declarations
- Build internal port list (visible from within the node)
- Parse port expressions into an external port list (visible when instantiating the node)
Structs
An external port.
A port expression associating an external port with an internal port.
An internal port.
Additional internal port details.
List of internal and external ports of a node.
Enums
A select operation into an internal port.
Traits
Anything that can be converted to a PortedNode.
Marker trait for AST nodes that have ports.