Module nvml_wrapper_sys::bindings::field_id

Constants

• NVML_FI_DEV_C2C_LINK_COUNT
• NVML_FI_DEV_C2C_LINK_GET_MAX_BW
• NVML_FI_DEV_C2C_LINK_GET_STATUS
• NVML_FI_DEV_ECC_CURRENT
• NVML_FI_DEV_ECC_DBE_AGG_CBU
• NVML_FI_DEV_ECC_DBE_AGG_DEV
• NVML_FI_DEV_ECC_DBE_AGG_L1
• NVML_FI_DEV_ECC_DBE_AGG_L2
• NVML_FI_DEV_ECC_DBE_AGG_REG
• NVML_FI_DEV_ECC_DBE_AGG_TEX
• NVML_FI_DEV_ECC_DBE_AGG_TOTAL
• NVML_FI_DEV_ECC_DBE_VOL_CBU
• NVML_FI_DEV_ECC_DBE_VOL_DEV
• NVML_FI_DEV_ECC_DBE_VOL_L1
• NVML_FI_DEV_ECC_DBE_VOL_L2
• NVML_FI_DEV_ECC_DBE_VOL_REG
• NVML_FI_DEV_ECC_DBE_VOL_TEX
• NVML_FI_DEV_ECC_DBE_VOL_TOTAL
• NVML_FI_DEV_ECC_PENDING
• NVML_FI_DEV_ECC_SBE_AGG_DEV
• NVML_FI_DEV_ECC_SBE_AGG_L1
• NVML_FI_DEV_ECC_SBE_AGG_L2
• NVML_FI_DEV_ECC_SBE_AGG_REG
• NVML_FI_DEV_ECC_SBE_AGG_TEX
• NVML_FI_DEV_ECC_SBE_AGG_TOTAL
• NVML_FI_DEV_ECC_SBE_VOL_DEV
• NVML_FI_DEV_ECC_SBE_VOL_L1
• NVML_FI_DEV_ECC_SBE_VOL_L2
• NVML_FI_DEV_ECC_SBE_VOL_REG
• NVML_FI_DEV_ECC_SBE_VOL_TEX
• NVML_FI_DEV_ECC_SBE_VOL_TOTAL
• NVML_FI_DEV_ENERGY
• NVML_FI_DEV_IS_RESETLESS_MIG_SUPPORTED
• NVML_FI_DEV_MEMORY_TEMP
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L6
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L7
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L8
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L9
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L10
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L11
• NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L6
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L7
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L8
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L9
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L10
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L11
• NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11
• NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11
• NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11
• NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL
• NVML_FI_DEV_NVLINK_ERROR_DL_CRC
• NVML_FI_DEV_NVLINK_ERROR_DL_RECOVERY
• NVML_FI_DEV_NVLINK_ERROR_DL_REPLAY
• NVML_FI_DEV_NVLINK_GET_POWER_STATE
• NVML_FI_DEV_NVLINK_GET_POWER_THRESHOLD
• NVML_FI_DEV_NVLINK_GET_SPEED
• NVML_FI_DEV_NVLINK_GET_STATE
• NVML_FI_DEV_NVLINK_GET_VERSION
• NVML_FI_DEV_NVLINK_LINK_COUNT
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11
• NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL
• NVML_FI_DEV_NVLINK_REMOTE_NVLINK_ID
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11
• NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL
• NVML_FI_DEV_NVLINK_SPEED_MBPS_COMMON
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L0
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L1
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L2
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L3
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L4
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L5
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L6
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L7
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L8
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L9
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L10
• NVML_FI_DEV_NVLINK_SPEED_MBPS_L11
• NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX
• NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX
• NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX
• NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX
• NVML_FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT
• NVML_FI_DEV_PCIE_COUNT_BAD_DLLP
• NVML_FI_DEV_PCIE_COUNT_BAD_TLP
• NVML_FI_DEV_PCIE_COUNT_CORRECTABLE_ERRORS
• NVML_FI_DEV_PCIE_COUNT_FATAL_ERROR
• NVML_FI_DEV_PCIE_COUNT_LANE_ERROR
• NVML_FI_DEV_PCIE_COUNT_LCRC_ERROR
• NVML_FI_DEV_PCIE_COUNT_NAKS_RECEIVED
• NVML_FI_DEV_PCIE_COUNT_NAKS_SENT
• NVML_FI_DEV_PCIE_COUNT_NON_FATAL_ERROR
• NVML_FI_DEV_PCIE_COUNT_RECEIVER_ERROR
• NVML_FI_DEV_PCIE_COUNT_UNSUPPORTED_REQ
• NVML_FI_DEV_PCIE_L0_TO_RECOVERY_COUNTER
• NVML_FI_DEV_PCIE_REPLAY_COUNTER
• NVML_FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER
• NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT
• NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION
• NVML_FI_DEV_PERF_POLICY_POWER
• NVML_FI_DEV_PERF_POLICY_RELIABILITY
• NVML_FI_DEV_PERF_POLICY_SYNC_BOOST
• NVML_FI_DEV_PERF_POLICY_THERMAL
• NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS
• NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS
• NVML_FI_DEV_POWER_AVERAGE
• NVML_FI_DEV_POWER_CURRENT_LIMIT
• NVML_FI_DEV_POWER_DEFAULT_LIMIT
• NVML_FI_DEV_POWER_INSTANT
• NVML_FI_DEV_POWER_MAX_LIMIT
• NVML_FI_DEV_POWER_MIN_LIMIT
• NVML_FI_DEV_POWER_REQUESTED_LIMIT
• NVML_FI_DEV_REMAPPED_COR
• NVML_FI_DEV_REMAPPED_FAILURE
• NVML_FI_DEV_REMAPPED_PENDING
• NVML_FI_DEV_REMAPPED_UNC
• NVML_FI_DEV_RETIRED_DBE
• NVML_FI_DEV_RETIRED_PENDING
• NVML_FI_DEV_RETIRED_PENDING_DBE
• NVML_FI_DEV_RETIRED_PENDING_SBE
• NVML_FI_DEV_RETIRED_SBE
• NVML_FI_DEV_TEMPERATURE_GPU_MAX_TLIMIT
• NVML_FI_DEV_TEMPERATURE_MEM_MAX_TLIMIT
• NVML_FI_DEV_TEMPERATURE_SHUTDOWN_TLIMIT
• NVML_FI_DEV_TEMPERATURE_SLOWDOWN_TLIMIT
• NVML_FI_DEV_TOTAL_ENERGY_CONSUMPTION
• NVML_FI_MAX