Expand description
Use these constants to populate the structs::device::FieldId newtype.
Constantsยง
- NVML_
FI_ DEV_ C2C_ LINK_ COUNT - NVML_
FI_ DEV_ C2C_ LINK_ GET_ MAX_ BW - NVML_
FI_ DEV_ C2C_ LINK_ GET_ STATUS - NVML_
FI_ DEV_ ECC_ CURRENT - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ CBU - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ DEV - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ L1 - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ L2 - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ REG - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ TEX - NVML_
FI_ DEV_ ECC_ DBE_ AGG_ TOTAL - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ CBU - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ DEV - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ L1 - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ L2 - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ REG - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ TEX - NVML_
FI_ DEV_ ECC_ DBE_ VOL_ TOTAL - NVML_
FI_ DEV_ ECC_ PENDING - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ DEV - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ L1 - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ L2 - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ REG - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ TEX - NVML_
FI_ DEV_ ECC_ SBE_ AGG_ TOTAL - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ DEV - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ L1 - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ L2 - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ REG - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ TEX - NVML_
FI_ DEV_ ECC_ SBE_ VOL_ TOTAL - NVML_
FI_ DEV_ ENERGY - NVML_
FI_ DEV_ IS_ RESETLESS_ MIG_ SUPPORTED - NVML_
FI_ DEV_ MEMORY_ TEMP - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L0 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L1 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L2 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L3 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L4 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L5 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L6 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L7 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L8 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L9 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L10 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ L11 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C0_ TOTAL - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L0 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L1 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L2 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L3 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L4 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L5 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L6 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L7 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L8 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L9 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L10 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ L11 - NVML_
FI_ DEV_ NVLINK_ BANDWIDTH_ C1_ TOTAL - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ CRC_ DATA_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ CRC_ FLIT_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ ECC_ DATA_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ ERROR_ DL_ CRC - NVML_
FI_ DEV_ NVLINK_ ERROR_ DL_ RECOVERY - NVML_
FI_ DEV_ NVLINK_ ERROR_ DL_ REPLAY - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ STATE - NVML_
FI_ DEV_ NVLINK_ GET_ POWER_ THRESHOLD - NVML_
FI_ DEV_ NVLINK_ GET_ SPEED - NVML_
FI_ DEV_ NVLINK_ GET_ STATE - NVML_
FI_ DEV_ NVLINK_ GET_ VERSION - NVML_
FI_ DEV_ NVLINK_ LINK_ COUNT - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ RECOVERY_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ REMOTE_ NVLINK_ ID - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L0 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L1 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L2 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L3 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L4 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L5 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L6 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L7 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L8 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L9 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L10 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ L11 - NVML_
FI_ DEV_ NVLINK_ REPLAY_ ERROR_ COUNT_ TOTAL - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ COMMON - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L0 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L1 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L2 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L3 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L4 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L5 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L6 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L7 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L8 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L9 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L10 - NVML_
FI_ DEV_ NVLINK_ SPEED_ MBPS_ L11 - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ DATA_ RX - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ DATA_ TX - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ RAW_ RX - NVML_
FI_ DEV_ NVLINK_ THROUGHPUT_ RAW_ TX - NVML_
FI_ DEV_ NVSWITCH_ CONNECTED_ LINK_ COUNT - NVML_
FI_ DEV_ PCIE_ COUNT_ BAD_ DLLP - NVML_
FI_ DEV_ PCIE_ COUNT_ BAD_ TLP - NVML_
FI_ DEV_ PCIE_ COUNT_ CORRECTABLE_ ERRORS - NVML_
FI_ DEV_ PCIE_ COUNT_ FATAL_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ LANE_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ LCRC_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ NAKS_ RECEIVED - NVML_
FI_ DEV_ PCIE_ COUNT_ NAKS_ SENT - NVML_
FI_ DEV_ PCIE_ COUNT_ NON_ FATAL_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ RECEIVER_ ERROR - NVML_
FI_ DEV_ PCIE_ COUNT_ UNSUPPORTED_ REQ - NVML_
FI_ DEV_ PCIE_ L0_ TO_ RECOVERY_ COUNTER - NVML_
FI_ DEV_ PCIE_ REPLAY_ COUNTER - NVML_
FI_ DEV_ PCIE_ REPLAY_ ROLLOVER_ COUNTER - NVML_
FI_ DEV_ PERF_ POLICY_ BOARD_ LIMIT - NVML_
FI_ DEV_ PERF_ POLICY_ LOW_ UTILIZATION - NVML_
FI_ DEV_ PERF_ POLICY_ POWER - NVML_
FI_ DEV_ PERF_ POLICY_ RELIABILITY - NVML_
FI_ DEV_ PERF_ POLICY_ SYNC_ BOOST - NVML_
FI_ DEV_ PERF_ POLICY_ THERMAL - NVML_
FI_ DEV_ PERF_ POLICY_ TOTAL_ APP_ CLOCKS - NVML_
FI_ DEV_ PERF_ POLICY_ TOTAL_ BASE_ CLOCKS - NVML_
FI_ DEV_ POWER_ AVERAGE - NVML_
FI_ DEV_ POWER_ CURRENT_ LIMIT - NVML_
FI_ DEV_ POWER_ DEFAULT_ LIMIT - NVML_
FI_ DEV_ POWER_ INSTANT - NVML_
FI_ DEV_ POWER_ MAX_ LIMIT - NVML_
FI_ DEV_ POWER_ MIN_ LIMIT - NVML_
FI_ DEV_ POWER_ REQUESTED_ LIMIT - NVML_
FI_ DEV_ REMAPPED_ COR - NVML_
FI_ DEV_ REMAPPED_ FAILURE - NVML_
FI_ DEV_ REMAPPED_ PENDING - NVML_
FI_ DEV_ REMAPPED_ UNC - NVML_
FI_ DEV_ RETIRED_ DBE - NVML_
FI_ DEV_ RETIRED_ PENDING - NVML_
FI_ DEV_ RETIRED_ PENDING_ DBE - NVML_
FI_ DEV_ RETIRED_ PENDING_ SBE - NVML_
FI_ DEV_ RETIRED_ SBE - NVML_
FI_ DEV_ TEMPERATURE_ GPU_ MAX_ TLIMIT - NVML_
FI_ DEV_ TEMPERATURE_ MEM_ MAX_ TLIMIT - NVML_
FI_ DEV_ TEMPERATURE_ SHUTDOWN_ TLIMIT - NVML_
FI_ DEV_ TEMPERATURE_ SLOWDOWN_ TLIMIT - NVML_
FI_ DEV_ TOTAL_ ENERGY_ CONSUMPTION - NVML_
FI_ MAX