Crate riscv

Low level access to RISC-V processors

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.60 and up. It might compile with older versions but that may change in any new patch release.

Features

This crate provides:

• Access to core registers like mstatus or mcause.
• Interrupt manipulation mechanisms.
• Wrappers around assembly instructions like WFI.

Optional features

s-mode

This feature re-exports in interrupt S-mode interrupt functions defined in interrupt::supervisor. By default, the crate assumes that the target is running in M-mode. Thus, interrupt re-exports the M-mode functions defined in interrupt::machine.

critical-section-single-hart

This feature enables a critical-section implementation suitable for single-hart targets, based on disabling interrupts globally. This feature uses S-mode interrupt handling if the s-mode feature is enabled, and M-mode otherwise.

It is unsound to enable it on multi-hart targets, and may cause functional problems in systems where some interrupts must NOT be disabled or critical sections are managed as part of an RTOS. In these cases, you should use a target-specific implementation instead, typically provided by a HAL or RTOS crate.

Modules

• asm
  Assembly instructions
• bits
• delay
  Delay devices and providers
• interrupt
  Interrupts
• register
  RISC-V CSR’s
• result

Macros

• clear
  Convenience macro around the csrrc assembly instruction to clear the CSR register.
• clear_csr
  Convenience macro to define field clear functions for a CSR type.
• clear_rv32
  RV32: Convenience macro around the csrrc assembly instruction to clear the CSR register.
• csr
  Helper macro to define a CSR type.
• csr_field_enum
• paste
• read_composite_csr
  Convenience macro to read a composite value from a CSR register.
• read_csr
  Convenience macro to wrap the csrrs assembly instruction for reading a CSR register.
• read_csr_as
  Convenience macro to read a CSR register value as a register type.
• read_csr_as_rv32
  RV32: Convenience macro to read a CSR register value as a register type.
• read_csr_as_usize
  Convenience macro to read a CSR register value as a usize.
• read_csr_as_usize_rv32
  RV32: Convenience macro to read a CSR register value as a usize.
• read_csr_rv32
  RV32: Convenience macro to wrap the csrrs assembly instruction for reading a CSR register.
• read_only_csr
  Helper macro to create a read-only CSR type.
• read_only_csr_field
  Defines field accesor functions for a read-only CSR type.
• read_write_csr
  Helper macro to create a read-write CSR type.
• read_write_csr_field
  Defines field accesor functions for a read-write CSR type.
• set
  Convenience macro around the csrrs assembly instruction to set the CSR register.
• set_clear_csr
  Convenience macro to define field setter and clear functions for a CSR type.
• set_csr
  Convenience macro to define field setter functions for a CSR type.
• set_rv32
  RV32: Convenience macro around the csrrs assembly instruction to set the CSR register.
• singleton
  Macro to create a mutable reference to a statically allocated value
• write_csr
  Convenience macro to wrap the csrrw assembly instruction for writing to CSR registers.
• write_csr_as
  Convenience macro to write a value with bits to a CSR
• write_csr_as_rv32
  Convenience macro to write a value to a CSR register.
• write_csr_as_usize
  Convenience macro to write a usize value to a CSR register.
• write_csr_as_usize_rv32
  RV32: Convenience macro to write a usize value to a CSR register.
• write_csr_rv32
  RV32: Convenience macro to wrap the csrrw assembly instruction for writing to CSR registers.
• write_only_csr
  Helper macro to create a read-only CSR type.
• write_only_csr_field
  Defines field accesor functions for a write-only CSR type.

Traits

• CoreInterruptNumber
  Marker trait for enums of target-specific core interrupt numbers.
• ExceptionNumber
  Trait for enums of target-specific exception numbers.
• ExternalInterruptNumber
  Marker trait for enums of target-specific external interrupt numbers.
• HartIdNumber
  Trait for enums of HART identifiers.
• InterruptNumber
  Trait for enums of target-specific interrupt numbers.
• PriorityNumber
  Trait for enums of priority levels.

Attribute Macros

• pac_enum
  Attribute-like macro that implements the traits of the riscv-pac crate for a given enum.