sbi_spec/
pmu.rs

1//! Chapter 11. Performance Monitoring Unit Extension (EID #0x504D55 "PMU").
2
3/// Extension ID for Performance Monitoring Unit extension.
4pub const EID_PMU: usize = crate::eid_from_str("PMU") as _;
5pub use fid::*;
6
7/// Declared in §11.11.
8mod fid {
9    /// Function ID to get the number of counters, both hardware and firmware.
10    ///
11    /// Declared in §11.6.
12    pub const NUM_COUNTERS: usize = 0;
13    /// Function ID to get details about the specified counter.
14    ///
15    /// Declared in §11.7.
16    pub const COUNTER_GET_INFO: usize = 1;
17    /// Function ID to find and configure a counter from a set of counters.
18    ///
19    /// Declared in §11.8.
20    pub const COUNTER_CONFIG_MATCHING: usize = 2;
21    /// Function ID to start or enable a set of counters on the calling hart with the specified initial value.
22    ///
23    /// Declared in §11.9.
24    pub const COUNTER_START: usize = 3;
25    /// Function ID to stop or disable a set of counters on the calling hart.
26    ///
27    /// Declared in §11.10.
28    pub const COUNTER_STOP: usize = 4;
29    /// Function ID to provide the current value of a firmware counter.
30    ///
31    /// Declared in §11.11.
32    pub const COUNTER_FW_READ: usize = 5;
33    /// Function ID to provide the upper 32 bits from the value of the current firmware counter.
34    ///
35    /// Declared in §11.12.
36    pub const COUNTER_FW_READ_HI: usize = 6;
37    /// Function ID to set and enable the PMU snapshot shared memory.
38    ///
39    /// Declared in §11.13.
40    pub const SNAPSHOT_SET_SHMEM: usize = 7;
41}
42
43/// PMU Event Types.
44///
45/// Declared in §11.
46pub mod event_type {
47    /// Type for all hardware general events.
48    ///
49    /// Declared in §11.1.
50    pub const HARDWARE_GENERAL: usize = 0;
51    /// Type for all hardware cache events.
52    ///
53    /// Declared in §11.2.
54    pub const HARDWARE_CACHE: usize = 1;
55    /// Type for all hardware raw events.
56    ///
57    /// Declared in §11.3.
58    pub const HARDWARE_RAW: usize = 2;
59    /// Type for all firmware events.
60    ///
61    /// Declared in §11.4.
62    pub const FIRMWARE: usize = 15;
63}
64
65/// Hardware General Event Codes.
66///
67/// Declared in §11.1.
68pub mod hardware_event {
69    /// Unused event because event_idx cannot be zero.
70    pub const NO_EVENT: usize = 0;
71    /// Event for each CPU cycle.
72    pub const CPU_CYCLES: usize = 1;
73    /// Event for each completed instruction.
74    pub const INSTRUCTIONS: usize = 2;
75    /// Event for cache hit.
76    pub const CACHE_REFERENCES: usize = 3;
77    /// Event for cache miss.
78    pub const CACHE_MISSES: usize = 4;
79    /// Event for a branch instruction.
80    pub const BRANCH_INSTRUCTIONS: usize = 5;
81    /// Event for a branch mis-prediction.
82    pub const BRANCH_MISSES: usize = 6;
83    /// Event for each BUS cycle.
84    pub const BUS_CYCLES: usize = 7;
85    /// Event for a stalled cycle in micro-architecture frontend.
86    pub const STALLED_CYCLES_FRONTEND: usize = 8;
87    /// Event for a stalled cycle in micro-architecture backend.
88    pub const STALLED_CYCLES_BACKEND: usize = 9;
89    /// Event for each reference CPU cycle.
90    pub const REF_CPU_CYCLES: usize = 10;
91}
92
93/// Hardware Cache Event ID.
94///
95/// Declared in §11.2.
96pub mod cache_event {
97    /// Level 1 data cache event.
98    pub const L1D: usize = 0;
99    /// Level 1 instruction cache event.
100    pub const L1I: usize = 1;
101    /// Last level cache event.
102    pub const LL: usize = 2;
103    /// Data TLB event.
104    pub const DTLB: usize = 3;
105    /// Instruction TLB event.
106    pub const ITLB: usize = 4;
107    /// Branch predictor unit event.
108    pub const BPU: usize = 5;
109    /// NUMA node cache event.
110    pub const NODE: usize = 6;
111}
112
113/// Hardware Cache Operation ID.
114///
115/// Declared in §11.2.
116pub mod cache_operation {
117    /// Read cache line.
118    pub const READ: usize = 0;
119    /// Write cache line.
120    pub const WRITE: usize = 1;
121    /// Prefetch cache line.
122    pub const PREFETCH: usize = 2;
123}
124
125/// Hardware Cache Operation Result ID.
126///
127/// Declared in §11.2.
128pub mod cache_result {
129    /// Cache access.
130    pub const ACCESS: usize = 0;
131    /// Cache miss.
132    pub const MISS: usize = 1;
133}
134
135/// Firmware Event Codes.
136///
137/// Declared in §11.4.
138pub mod firmware_event {
139    /// Misaligned load trap event.
140    pub const MISALIGNED_LOAD: usize = 0;
141    /// Misaligned store trap event.
142    pub const MISALIGNED_STORE: usize = 1;
143    /// Load access trap event.
144    pub const ACCESS_LOAD: usize = 2;
145    /// Store access trap event.
146    pub const ACCESS_STORE: usize = 3;
147    /// Illegal instruction trap event.
148    pub const ILLEGAL_INSN: usize = 4;
149    /// Set timer event.
150    pub const SET_TIMER: usize = 5;
151    /// Sent IPI to other HART event.
152    pub const IPI_SENT: usize = 6;
153    /// Received IPI from other HART event.
154    pub const IPI_RECEIVED: usize = 7;
155    /// Sent FENCE.I request to other HART event.
156    pub const FENCE_I_SENT: usize = 8;
157    /// Received FENCE.I request from other HART event.
158    pub const FENCE_I_RECEIVED: usize = 9;
159    /// Sent SFENCE.VMA request to other HART event.
160    pub const SFENCE_VMA_SENT: usize = 10;
161    /// Received SFENCE.VMA request from other HART event.
162    pub const SFENCE_VMA_RECEIVED: usize = 11;
163    /// Sent SFENCE.VMA with ASID request to other HART event.
164    pub const SFENCE_VMA_ASID_SENT: usize = 12;
165    /// Received SFENCE.VMA with ASID request from other HART event.
166    pub const SFENCE_VMA_ASID_RECEIVED: usize = 13;
167    /// Sent HFENCE.GVMA request to other HART event.
168    pub const HFENCE_GVMA_SENT: usize = 14;
169    /// Received HFENCE.GVMA request from other HART event.
170    pub const HFENCE_GVMA_RECEIVED: usize = 15;
171    /// Sent HFENCE.GVMA with VMID request to other HART event.
172    pub const HFENCE_GVMA_VMID_SENT: usize = 16;
173    /// Received HFENCE.GVMA with VMID request from other HART event.
174    pub const HFENCE_GVMA_VMID_RECEIVED: usize = 17;
175    /// Sent HFENCE.VVMA request to other HART event.
176    pub const HFENCE_VVMA_SENT: usize = 18;
177    /// Received HFENCE.VVMA request from other HART event.
178    pub const HFENCE_VVMA_RECEIVED: usize = 19;
179    /// Sent HFENCE.VVMA with ASID request to other HART event.
180    pub const HFENCE_VVMA_ASID_SENT: usize = 20;
181    /// Received HFENCE.VVMA with ASID request from other HART event.
182    pub const HFENCE_VVMA_ASID_RECEIVED: usize = 21;
183    /// RISC-V platform specific firmware events.
184    ///
185    /// The `event_data` configuration (or parameter) contains the event encoding.
186    pub const PLATFORM: usize = 65535;
187}
188
189/// Size of shared memory on PMU extension set by supervisor software for current hart.
190pub mod shmem_size {
191    /// Size of PMU snapshot shared memory.
192    ///
193    /// PMU snapshot memory size must be 4096 size on all architecture XLEN configurations.
194    pub const SIZE: usize = 4096;
195}
sbi_spec/pmu.rs

sbi_spec/
pmu.rs
