sparreal_kernel/platform_if/
mod.rs

1pub use rdrive::register::DriverRegisterSlice;
2use sparreal_macros::api_trait;
3
4use crate::mem::KernelRegions;
5
6#[api_trait]
7pub trait Platform {
8    fn kernel_regions() -> KernelRegions;
9    fn kstack_size() -> usize;
10    fn cpu_id() -> usize;
11    fn cpu_context_size() -> usize;
12
13    /// # Safety
14    ///
15    ///
16    unsafe fn get_current_tcb_addr() -> *mut u8;
17
18    /// # Safety
19    ///
20    ///
21    unsafe fn set_current_tcb_addr(addr: *mut u8);
22
23    /// # Safety
24    ///
25    /// `ctx_ptr` 是有效的上下文指针
26    unsafe fn cpu_context_sp(ctx_ptr: *const u8) -> usize;
27
28    /// # Safety
29    ///
30    /// `ctx_ptr` 是有效的上下文指针
31    unsafe fn cpu_context_set_sp(ctx_ptr: *const u8, sp: usize);
32
33    /// # Safety
34    ///
35    /// `ctx_ptr` 是有效的上下文指针
36    unsafe fn cpu_context_set_pc(ctx_ptr: *const u8, pc: usize);
37
38    /// # Safety
39    ///
40    ///
41    unsafe fn cpu_context_switch(prev_tcb: *mut u8, next_tcb: *mut u8);
42
43    fn wait_for_interrupt();
44
45    fn irq_all_enable();
46    fn irq_all_disable();
47    fn irq_all_is_enabled() -> bool;
48
49    fn on_boot_success() {}
50    fn shutdown() -> !;
51    fn debug_put(b: u8);
52
53    fn dcache_range(op: CacheOp, addr: usize, size: usize);
54
55    fn driver_registers() -> DriverRegisterSlice;
56}
57
58#[cfg(feature = "mmu")]
59#[api_trait]
60pub trait MMU {
61    fn set_kernel_table(addr: usize);
62    fn get_kernel_table() -> usize;
63    fn set_user_table(addr: usize);
64    fn get_user_table() -> usize;
65
66    /// flush tlb
67    /// # Safety
68    /// addr must be page aligned
69    unsafe fn flush_tlb(addr: *const u8);
70    fn flush_tlb_all();
71    fn page_size() -> usize;
72    fn table_level() -> usize;
73    fn new_pte(config: page_table_generic::PTEGeneric) -> usize;
74    fn read_pte(pte: usize) -> page_table_generic::PTEGeneric;
75    fn enable_mmu(stack_top: usize, jump_to: usize) -> !;
76}
77
78#[repr(C)]
79#[derive(Debug, Clone, Copy)]
80pub enum CacheOp {
81    /// Write back to memory
82    Clean,
83    /// Invalidate cache
84    Invalidate,
85    /// Clean and invalidate
86    CleanAndInvalidate,
87}