stm32_fmc/devices/
as4c4m16sa.rs

1/// Alliance Memory AS4C4M16SA SDRAM
2/// <https://www.alliancememory.com/wp-content/uploads/pdf/dram/Alliance_Memory_64M-AS4C4M16SA-CI_v5.0_October_2018.pdf>
3#[allow(unused)]
4
5pub mod as4c4m16sa_6 {
6    use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming};
7
8    // Burst length
9    const BURST_LENGTH_1: u16 = 0b0000_0000_0000_0000; // A2 = 0, A1 = 0, A0 = 0
10    const BURST_LENGTH_2: u16 = 0b0000_0000_0000_0001; // A2 = 0, A1 = 0, A0 = 1
11    const BURST_LENGTH_4: u16 = 0b0000_0000_0000_0010; // A2 = 0, A1 = 1, A0 = 0
12    const BURST_LENGTH_8: u16 = 0b0000_0000_0000_0011; // A2 = 0, A1 = 1, A0 = 1
13    const BURST_LENGTH_FULL_PAGE_SEQUENTIAL: u16 = 0b0000_0000_0000_0111; // A2 = 1, A1 = 1, A0 = 1
14
15    // Burst type
16    const BURST_TYPE_SEQUENTIAL: u16 = 0b0000_0000_0000_0000; // A3 = 0
17    const BURST_TYPE_INTERLEAVED: u16 = 0b0000_0000_0000_1000; // A3 = 1
18
19    // CAS Latency
20    const CAS_LATENCY_2: u16 = 0b0000_0000_0010_0000; // A6 = 0, A5 = 1, A4 = 0
21    const CAS_LATENCY_3: u16 = 0b0000_0000_0011_0000; // A6 = 0, A5 = 1, A4 = 1
22
23    // Test mode
24    const TEST_MODE_NORMAL: u16 = 0b0000_0000_0000_0000; // A8 = 0, A7 = 0
25    const TEST_MODE_VENDOR_USE_ONLY_10: u16 = 0b0000_0001_0000_0000; // A8 = 1, A7 = 0
26    const TEST_MODE_VENDOR_USE_ONLY_01: u16 = 0b0000_0000_1000_0000; // A8 = 0, A7 = 1
27
28    // Write burst length
29    const WRITE_BURST_LENGTH_BURST: u16 = 0b0000_0000_0000_0000; // A9 = 0
30    const WRITE_BURST_LENGTH_SINGLE_BIT: u16 = 0b0000_0010_0000_0000; // A9 = 1
31
32    // RFU* = 0
33
34    /// As4c4m16sa
35    #[derive(Clone, Copy, Debug, PartialEq)]
36    pub struct As4c4m16sa {}
37
38    impl SdramChip for As4c4m16sa {
39        /// Value of the mode register
40        const MODE_REGISTER: u16 = BURST_LENGTH_1
41            | BURST_TYPE_SEQUENTIAL
42            | CAS_LATENCY_3
43            | TEST_MODE_NORMAL
44            | WRITE_BURST_LENGTH_SINGLE_BIT;
45
46        // 166MHz = 6.024ns per clock cycle
47
48        /// Timing Parameters
49        const TIMING: SdramTiming = SdramTiming {
50            startup_delay_ns: 200_000,    // 200 µs
51            max_sd_clock_hz: 166_000_000, // 166 MHz
52            refresh_period_ns: 15_625,    // 64ms / (4096 rows) = 15625ns
53            mode_register_to_active: 2,   // tMRD = 2 cycles
54            exit_self_refresh: 11, // tXSR = 62ns, cycles = ceil(166000000*(62*10^(-9)))
55            active_to_precharge: 7, // tRAS = 42ns cycles = ceil(166000000*(42*10^(-9)))
56            row_cycle: 10, // tRC = 60ns cycles = ceil(166000000*(60*10^(-9)))
57            row_precharge: 3, // tRP = 18ns cycles = ceil(166000000*(18*10^(-9)))
58            row_to_column: 3, // tRCD = 18ns cycles = ceil(166000000*(18*10^(-9)))
59        };
60
61        /// SDRAM controller configuration
62        const CONFIG: SdramConfiguration = SdramConfiguration {
63            column_bits: 8,        // A0-A7
64            row_bits: 13,          // A0-A12
65            memory_data_width: 16, // 16-bit
66            internal_banks: 4,     // 4 internal banks
67            cas_latency: 3,        // CAS latency = 3
68            write_protection: false,
69            read_burst: true,
70            read_pipe_delay_cycles: 0,
71        };
72    }
73}
stm32_fmc/devices/as4c4m16sa.rs

stm32_fmc/devices/
as4c4m16sa.rs
