stm32_fmc/devices/
is42s32400f.rs

1/// ISI IS42S32400F SDRAM
2#[allow(unused)]
3
4/// Speed Grade 6
5pub mod is42s32400f_6 {
6    use crate::sdram::{SdramChip, SdramConfiguration, SdramTiming};
7
8    const BURST_LENGTH_1: u16 = 0x0000;
9    const BURST_LENGTH_2: u16 = 0x0001;
10    const BURST_LENGTH_4: u16 = 0x0002;
11    const BURST_LENGTH_8: u16 = 0x0004;
12    const BURST_TYPE_SEQUENTIAL: u16 = 0x0000;
13    const BURST_TYPE_INTERLEAVED: u16 = 0x0008;
14    const CAS_LATENCY_2: u16 = 0x0020;
15    const CAS_LATENCY_3: u16 = 0x0030;
16    const OPERATING_MODE_STANDARD: u16 = 0x0000;
17    const WRITEBURST_MODE_PROGRAMMED: u16 = 0x0000;
18    const WRITEBURST_MODE_SINGLE: u16 = 0x0200;
19
20    /// Is42s32400f with Speed Grade 6
21    #[derive(Clone, Copy, Debug, PartialEq)]
22    pub struct Is42s32400f6 {}
23
24    impl SdramChip for Is42s32400f6 {
25        /// Value of the mode register
26        const MODE_REGISTER: u16 = BURST_LENGTH_1
27            | BURST_TYPE_SEQUENTIAL
28            | CAS_LATENCY_3
29            | OPERATING_MODE_STANDARD
30            | WRITEBURST_MODE_SINGLE;
31
32        /// Timing Parameters
33        const TIMING: SdramTiming = SdramTiming {
34            startup_delay_ns: 100_000,    // 100 µs
35            max_sd_clock_hz: 100_000_000, // 100 MHz
36            refresh_period_ns: 15_625,    // 64ms / (4096 rows) = 15625ns
37            mode_register_to_active: 2,   // tMRD = 2 cycles
38            exit_self_refresh: 7,         // tXSR = 70ns
39            active_to_precharge: 4,       // tRAS = 42ns
40            row_cycle: 6,                 // tRC = 60ns
41            row_precharge: 2,             // tRP = 18ns
42            row_to_column: 2,             // tRCD = 18ns
43        };
44
45        /// SDRAM controller configuration
46        const CONFIG: SdramConfiguration = SdramConfiguration {
47            column_bits: 8,
48            row_bits: 12,
49            memory_data_width: 32, // 32-bit
50            internal_banks: 4,     // 4 internal banks
51            cas_latency: 3,        // CAS latency = 3
52            write_protection: false,
53            read_burst: true,
54            read_pipe_delay_cycles: 0,
55        };
56    }
57}
stm32_fmc/devices/is42s32400f.rs

stm32_fmc/devices/
is42s32400f.rs
