Module stm32_metapac::timer::regs

Structs

• Arr16
  auto-reload register
• Arr32
  auto-reload register
• Bdtr
  break and dead-time register
• CcerAdv
  capture/compare enable register
• CcerGp
  capture/compare enable register
• CcmrInput
  capture/compare mode register 1 (input mode)
• CcmrOutput
  capture/compare mode register 2 (output mode)
• Ccr16
  capture/compare register 1
• Ccr32
  capture/compare register 1
• Cnt16
  counter
• Cnt32
  counter
• Cr1Basic
  control register 1
• Cr1Gp
  control register 1
• Cr2Adv
  control register 2
• Cr2Basic
  control register 2
• Cr2Gp
  control register 2
• Dcr
  DMA control register
• DierAdv
  DMA/Interrupt enable register
• DierBasic
  DMA/Interrupt enable register
• DierGp
  DMA/Interrupt enable register
• Dmar
  DMA address for full transfer
• EgrAdv
  event generation register
• EgrBasic
  event generation register
• EgrGp
  event generation register
• Psc
  prescaler
• Rcr
  repetition counter register
• Smcr
  slave mode control register
• SrAdv
  status register
• SrBasic
  status register
• SrGp
  status register