[−][src]Constant x86::msr::MSR_EMON_L3_CTR_CTL5
pub const MSR_EMON_L3_CTR_CTL5: u32 = 0x107d1;
FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2