Enum avr_device::atmega4809::evsys::channel3::GENERATOR_A

#[repr(u8)]
pub enum GENERATOR_A {
    OFF = 0,
    UPDI = 1,
    RTC_OVF = 6,
    RTC_CMP = 7,
    RTC_PIT0 = 8,
    RTC_PIT1 = 9,
    RTC_PIT2 = 10,
    RTC_PIT3 = 11,
    CCL_LUT0 = 16,
    CCL_LUT1 = 17,
    CCL_LUT2 = 18,
    CCL_LUT3 = 19,
    AC0_OUT = 32,
    ADC0_RESRDY = 36,
    PORT0_PIN0 = 64,
    PORT0_PIN1 = 65,
    PORT0_PIN2 = 66,
    PORT0_PIN3 = 67,
    PORT0_PIN4 = 68,
    PORT0_PIN5 = 69,
    PORT0_PIN6 = 70,
    PORT0_PIN7 = 71,
    PORT1_PIN0 = 72,
    PORT1_PIN1 = 73,
    PORT1_PIN2 = 74,
    PORT1_PIN3 = 75,
    PORT1_PIN4 = 76,
    PORT1_PIN5 = 77,
    PORT1_PIN6 = 78,
    PORT1_PIN7 = 79,
    USART0_XCK = 96,
    USART1_XCK = 97,
    USART2_XCK = 98,
    USART3_XCK = 99,
    SPI0_SCK = 104,
    TCA0_OVF_LUNF = 128,
    TCA0_HUNF = 129,
    TCA0_CMP0 = 132,
    TCA0_CMP1 = 133,
    TCA0_CMP2 = 134,
    TCB0_CAPT = 160,
    TCB1_CAPT = 162,
    TCB2_CAPT = 164,
    TCB3_CAPT = 166,
}

Generator selector

Value on reset: 0

Variants

OFF = 0

0: Off

UPDI = 1

1: Unified Program and Debug Interface

RTC_OVF = 6

6: Real Time Counter overflow

RTC_CMP = 7

7: Real Time Counter compare

RTC_PIT0 = 8

8: Periodic Interrupt Timer output 0

RTC_PIT1 = 9

9: Periodic Interrupt Timer output 1

RTC_PIT2 = 10

10: Periodic Interrupt Timer output 2

RTC_PIT3 = 11

11: Periodic Interrupt Timer output 3

CCL_LUT0 = 16

16: Configurable Custom Logic LUT0

CCL_LUT1 = 17

17: Configurable Custom Logic LUT1

CCL_LUT2 = 18

18: Configurable Custom Logic LUT2

CCL_LUT3 = 19

19: Configurable Custom Logic LUT3

AC0_OUT = 32

32: Analog Comparator 0 out

ADC0_RESRDY = 36

36: ADC 0 Result Ready Event

PORT0_PIN0 = 64

64: Port 0 Pin 0

PORT0_PIN1 = 65

65: Port 0 Pin 1

PORT0_PIN2 = 66

66: Port 0 Pin 2

PORT0_PIN3 = 67

67: Port 0 Pin 3

PORT0_PIN4 = 68

68: Port 0 Pin 4

PORT0_PIN5 = 69

69: Port 0 Pin 5

PORT0_PIN6 = 70

70: Port 0 Pin 6

PORT0_PIN7 = 71

71: Port 0 Pin 7

PORT1_PIN0 = 72

72: Port 1 Pin 0

PORT1_PIN1 = 73

73: Port 1 Pin 1

PORT1_PIN2 = 74

74: Port 1 Pin 2

PORT1_PIN3 = 75

75: Port 1 Pin 3

PORT1_PIN4 = 76

76: Port 1 Pin 4

PORT1_PIN5 = 77

77: Port 1 Pin 5

PORT1_PIN6 = 78

78: Port 1 Pin 6

PORT1_PIN7 = 79

79: Port 1 Pin 7

USART0_XCK = 96

96: USART 0 Xclock

USART1_XCK = 97

97: USART 1 Xclock

USART2_XCK = 98

98: USART 2 Xclock

USART3_XCK = 99

99: USART 3 Xclock

SPI0_SCK = 104

104: SPI 0 Sclock

TCA0_OVF_LUNF = 128

128: Timer/Counter A0 overflow / low byte underflow

TCA0_HUNF = 129

129: Timer/Counter A0 high byte underflow (split mode)

TCA0_CMP0 = 132

132: Timer/Counter A0 compare 0

TCA0_CMP1 = 133

133: Timer/Counter A0 compare 1

TCA0_CMP2 = 134

134: Timer/Counter A0 compare 2

TCB0_CAPT = 160

160: Timer/Counter B0 capture

TCB1_CAPT = 162

162: Timer/Counter B1 capture

TCB2_CAPT = 164

164: Timer/Counter B2 capture

TCB3_CAPT = 166

166: Timer/Counter B3 capture

Trait Implementations

impl Clone for GENERATOR_A

fn clone(&self) -> GENERATOR_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for GENERATOR_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<GENERATOR_A> for u8

fn from(variant: GENERATOR_A) -> Self

Converts to this type from the input type.

impl PartialEq for GENERATOR_A

fn eq(&self, other: &GENERATOR_A) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for GENERATOR_A

impl Eq for GENERATOR_A

impl StructuralPartialEq for GENERATOR_A