Enum bxcan::Interrupt

#[non_exhaustive]
pub enum Interrupt {
    TransmitMailboxEmpty = 1,
    Fifo0MessagePending = 2,
    Fifo0Full = 4,
    Fifo0Overrun = 8,
    Fifo1MessagePending = 16,
    Fifo1Full = 32,
    Fifo1Overrun = 64,
    Error = 32_768,
    Wakeup = 65_536,
    Sleep = 131_072,
}

bxCAN interrupt sources.

These can be individually enabled and disabled in the bxCAN peripheral. Note that the bxCAN peripheral only exposes 4 interrupts to the microcontroller:

• TX
• RX FIFO 1
• RX FIFO 2
• SCE (Status Change Error)

This means that some of the interrupts listed here will result in the same interrupt handler being invoked.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

TransmitMailboxEmpty = 1

Fires the TX interrupt when one of the transmit mailboxes returns to empty state.

This usually happens because its message was either transmitted successfully, or transmission was aborted successfully.

The interrupt handler must clear the interrupt condition by calling Can::clear_request_completed_flag or Can::clear_tx_interrupt.

Fifo0MessagePending = 2

Fires the RX FIFO 0 interrupt when FIFO 0 holds a message.

The interrupt handler must clear the interrupt condition by receiving all messages from the FIFO by calling Can::receive or Rx0::receive.

Fifo0Full = 4

Fires the RX FIFO 0 interrupt when FIFO 0 holds 3 incoming messages.

The interrupt handler must clear the interrupt condition by receiving at least one message from the FIFO (making it no longer “full”). This can be done by calling Can::receive or Rx0::receive.

Fifo0Overrun = 8

Fires the RX FIFO 0 interrupt when FIFO 0 drops an incoming message.

The interrupt handler must clear the interrupt condition by calling Can::receive or Rx0::receive (which will return an error).

Fifo1MessagePending = 16

Fires the RX FIFO 1 interrupt when FIFO 1 holds a message.

Behavior is otherwise identical to Self::Fifo0MessagePending.

Fifo1Full = 32

Fires the RX FIFO 1 interrupt when FIFO 1 holds 3 incoming messages.

Behavior is otherwise identical to Self::Fifo0Full.

Fifo1Overrun = 64

Fires the RX FIFO 1 interrupt when FIFO 1 drops an incoming message.

Behavior is otherwise identical to Self::Fifo0Overrun.

Error = 32_768

Wakeup = 65_536

Fires the SCE interrupt when an incoming CAN frame is detected while the peripheral is in sleep mode.

The interrupt handler must clear the interrupt condition by calling Can::clear_wakeup_interrupt.

Sleep = 131_072

Fires the SCE interrupt when the peripheral enters sleep mode.

The interrupt handler must clear the interrupt condition by calling Can::clear_sleep_interrupt.

Trait Implementations

impl BitOrAssign<Interrupt> for Interrupts

Adds an interrupt to the interrupt set.

fn bitor_assign(&mut self, rhs: Interrupt)

Performs the |= operation.

impl Clone for Interrupt

fn clone(&self) -> Interrupt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Interrupt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<Interrupt> for Interrupts

fn from(i: Interrupt) -> Self

Converts to this type from the input type.

impl PartialEq for Interrupt

fn eq(&self, other: &Interrupt) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Interrupt

impl Eq for Interrupt

impl StructuralPartialEq for Interrupt