Trait CoreMachine

pub trait CoreMachine {
    type REG: Register;
    type MEM: Memory<REG = Self::REG>;

    // Required methods
    fn pc(&self) -> &Self::REG;
    fn update_pc(&mut self, pc: Self::REG);
    fn commit_pc(&mut self);
    fn memory(&self) -> &Self::MEM;
    fn memory_mut(&mut self) -> &mut Self::MEM;
    fn registers(&self) -> &[Self::REG];
    fn set_register(&mut self, idx: usize, value: Self::REG);
    fn version(&self) -> u32;
    fn isa(&self) -> u8;
}

This is the core part of RISC-V that only deals with data part, it is extracted from Machine so we can handle lifetime logic in dynamic syscall support.

Required Associated Types

type REG: Register

type MEM: Memory<REG = Self::REG>

Required Methods

fn pc(&self) -> &Self::REG

fn update_pc(&mut self, pc: Self::REG)

fn commit_pc(&mut self)

fn memory(&self) -> &Self::MEM

fn memory_mut(&mut self) -> &mut Self::MEM

fn registers(&self) -> &[Self::REG]

fn set_register(&mut self, idx: usize, value: Self::REG)

fn version(&self) -> u32

fn isa(&self) -> u8

Implementors

impl<Inner: CoreMachine> CoreMachine for DefaultMachine<Inner>

type REG = <Inner as CoreMachine>::REG

type MEM = <Inner as CoreMachine>::MEM

impl<Inner: SupportMachine> CoreMachine for TraceMachine<Inner>

type REG = <Inner as CoreMachine>::REG

type MEM = <Inner as CoreMachine>::MEM

impl<R: Register, M: Memory<REG = R>> CoreMachine for DefaultCoreMachine<R, M>

type REG = R

type MEM = M