Enum cranelift_codegen::isa::x64::Inst
source · pub enum Inst {
Show 102 variants
Nop {
len: u8,
},
AluRmiR {
size: OperandSize,
op: AluRmiROpcode,
src1: Gpr,
src2: GprMemImm,
dst: WritableGpr,
},
AluRM {
size: OperandSize,
op: AluRmiROpcode,
src1_dst: SyntheticAmode,
src2: Gpr,
},
AluRmRVex {
size: OperandSize,
op: AluRmROpcode,
src1: Gpr,
src2: GprMem,
dst: WritableGpr,
},
AluConstOp {
op: AluRmiROpcode,
size: OperandSize,
dst: WritableGpr,
},
UnaryRmR {
size: OperandSize,
op: UnaryRmROpcode,
src: GprMem,
dst: WritableGpr,
},
UnaryRmRVex {
size: OperandSize,
op: UnaryRmRVexOpcode,
src: GprMem,
dst: WritableGpr,
},
UnaryRmRImmVex {
size: OperandSize,
op: UnaryRmRImmVexOpcode,
src: GprMem,
dst: WritableGpr,
imm: u8,
},
Not {
size: OperandSize,
src: Gpr,
dst: WritableGpr,
},
Neg {
size: OperandSize,
src: Gpr,
dst: WritableGpr,
},
Div {
size: OperandSize,
sign: DivSignedness,
trap: TrapCode,
divisor: GprMem,
dividend_lo: Gpr,
dividend_hi: Gpr,
dst_quotient: WritableGpr,
dst_remainder: WritableGpr,
},
Div8 {
sign: DivSignedness,
trap: TrapCode,
divisor: GprMem,
dividend: Gpr,
dst: WritableGpr,
},
Mul {
size: OperandSize,
signed: bool,
src1: Gpr,
src2: GprMem,
dst_lo: WritableGpr,
dst_hi: WritableGpr,
},
Mul8 {
signed: bool,
src1: Gpr,
src2: GprMem,
dst: WritableGpr,
},
IMul {
size: OperandSize,
src1: Gpr,
src2: GprMem,
dst: WritableGpr,
},
IMulImm {
size: OperandSize,
src1: GprMem,
src2: i32,
dst: WritableGpr,
},
CheckedSRemSeq {
size: OperandSize,
dividend_lo: Gpr,
dividend_hi: Gpr,
divisor: Gpr,
dst_quotient: WritableGpr,
dst_remainder: WritableGpr,
},
CheckedSRemSeq8 {
dividend: Gpr,
divisor: Gpr,
dst: WritableGpr,
},
SignExtendData {
size: OperandSize,
src: Gpr,
dst: WritableGpr,
},
Imm {
dst_size: OperandSize,
simm64: u64,
dst: WritableGpr,
},
MovRR {
size: OperandSize,
src: Gpr,
dst: WritableGpr,
},
MovFromPReg {
src: PReg,
dst: WritableGpr,
},
MovToPReg {
src: Gpr,
dst: PReg,
},
MovzxRmR {
ext_mode: ExtMode,
src: GprMem,
dst: WritableGpr,
},
Mov64MR {
src: SyntheticAmode,
dst: WritableGpr,
},
LoadEffectiveAddress {
addr: SyntheticAmode,
dst: WritableGpr,
size: OperandSize,
},
MovsxRmR {
ext_mode: ExtMode,
src: GprMem,
dst: WritableGpr,
},
MovImmM {
size: OperandSize,
simm32: i32,
dst: SyntheticAmode,
},
MovRM {
size: OperandSize,
src: Gpr,
dst: SyntheticAmode,
},
ShiftR {
size: OperandSize,
kind: ShiftKind,
src: Gpr,
num_bits: Imm8Gpr,
dst: WritableGpr,
},
XmmRmiReg {
opcode: SseOpcode,
src1: Xmm,
src2: XmmMemAlignedImm,
dst: WritableXmm,
},
CmpRmiR {
size: OperandSize,
opcode: CmpOpcode,
src: GprMemImm,
dst: Gpr,
},
Setcc {
cc: CC,
dst: WritableGpr,
},
Bswap {
size: OperandSize,
src: Gpr,
dst: WritableGpr,
},
Cmove {
size: OperandSize,
cc: CC,
consequent: GprMem,
alternative: Gpr,
dst: WritableGpr,
},
XmmCmove {
ty: Type,
cc: CC,
consequent: XmmMemAligned,
alternative: Xmm,
dst: WritableXmm,
},
Push64 {
src: GprMemImm,
},
Pop64 {
dst: WritableGpr,
},
StackProbeLoop {
tmp: Writable<Reg>,
frame_size: u32,
guard_size: u32,
},
XmmRmR {
op: SseOpcode,
src1: Xmm,
src2: XmmMemAligned,
dst: WritableXmm,
},
XmmRmRUnaligned {
op: SseOpcode,
src1: Xmm,
src2: XmmMem,
dst: WritableXmm,
},
XmmRmRBlend {
op: SseOpcode,
src1: Xmm,
src2: XmmMemAligned,
mask: Xmm,
dst: WritableXmm,
},
XmmRmiRVex {
op: AvxOpcode,
src1: Xmm,
src2: XmmMemImm,
dst: WritableXmm,
},
XmmRmRImmVex {
op: AvxOpcode,
src1: Xmm,
src2: XmmMem,
dst: WritableXmm,
imm: u8,
},
XmmVexPinsr {
op: AvxOpcode,
src1: Xmm,
src2: GprMem,
dst: WritableXmm,
imm: u8,
},
XmmRmRVex3 {
op: AvxOpcode,
src1: Xmm,
src2: Xmm,
src3: XmmMem,
dst: WritableXmm,
},
XmmRmRBlendVex {
op: AvxOpcode,
src1: Xmm,
src2: XmmMem,
mask: Xmm,
dst: WritableXmm,
},
XmmUnaryRmRVex {
op: AvxOpcode,
src: XmmMem,
dst: WritableXmm,
},
XmmUnaryRmRImmVex {
op: AvxOpcode,
src: XmmMem,
dst: WritableXmm,
imm: u8,
},
XmmMovRMVex {
op: AvxOpcode,
src: Xmm,
dst: SyntheticAmode,
},
XmmMovRMImmVex {
op: AvxOpcode,
src: Xmm,
dst: SyntheticAmode,
imm: u8,
},
XmmToGprImmVex {
op: AvxOpcode,
src: Xmm,
dst: WritableGpr,
imm: u8,
},
GprToXmmVex {
op: AvxOpcode,
src: GprMem,
dst: WritableXmm,
src_size: OperandSize,
},
XmmToGprVex {
op: AvxOpcode,
src: Xmm,
dst: WritableGpr,
dst_size: OperandSize,
},
XmmRmREvex {
op: Avx512Opcode,
src1: Xmm,
src2: XmmMem,
dst: WritableXmm,
},
XmmUnaryRmRImmEvex {
op: Avx512Opcode,
src: XmmMem,
dst: WritableXmm,
imm: u8,
},
XmmRmREvex3 {
op: Avx512Opcode,
src1: Xmm,
src2: Xmm,
src3: XmmMem,
dst: WritableXmm,
},
XmmUnaryRmR {
op: SseOpcode,
src: XmmMemAligned,
dst: WritableXmm,
},
XmmUnaryRmRUnaligned {
op: SseOpcode,
src: XmmMem,
dst: WritableXmm,
},
XmmUnaryRmRImm {
op: SseOpcode,
src: XmmMemAligned,
imm: u8,
dst: WritableXmm,
},
XmmUnaryRmREvex {
op: Avx512Opcode,
src: XmmMem,
dst: WritableXmm,
},
XmmMovRM {
op: SseOpcode,
src: Xmm,
dst: SyntheticAmode,
},
XmmMovRMImm {
op: SseOpcode,
src: Xmm,
dst: SyntheticAmode,
imm: u8,
},
XmmToGpr {
op: SseOpcode,
src: Xmm,
dst: WritableGpr,
dst_size: OperandSize,
},
XmmToGprImm {
op: SseOpcode,
src: Xmm,
dst: WritableGpr,
imm: u8,
},
GprToXmm {
op: SseOpcode,
src: GprMem,
dst: WritableXmm,
src_size: OperandSize,
},
CvtIntToFloat {
op: SseOpcode,
src1: Xmm,
src2: GprMem,
dst: WritableXmm,
src2_size: OperandSize,
},
CvtIntToFloatVex {
op: AvxOpcode,
src1: Xmm,
src2: GprMem,
dst: WritableXmm,
src2_size: OperandSize,
},
CvtUint64ToFloatSeq {
dst_size: OperandSize,
src: Gpr,
dst: WritableXmm,
tmp_gpr1: WritableGpr,
tmp_gpr2: WritableGpr,
},
CvtFloatToSintSeq {
dst_size: OperandSize,
src_size: OperandSize,
is_saturating: bool,
src: Xmm,
dst: WritableGpr,
tmp_gpr: WritableGpr,
tmp_xmm: WritableXmm,
},
CvtFloatToUintSeq {
dst_size: OperandSize,
src_size: OperandSize,
is_saturating: bool,
src: Xmm,
dst: WritableGpr,
tmp_gpr: WritableGpr,
tmp_xmm: WritableXmm,
tmp_xmm2: WritableXmm,
},
XmmMinMaxSeq {
size: OperandSize,
is_min: bool,
lhs: Xmm,
rhs: Xmm,
dst: WritableXmm,
},
XmmCmpRmR {
op: SseOpcode,
src: XmmMemAligned,
dst: Xmm,
},
XmmRmRImm {
op: SseOpcode,
src1: Reg,
src2: RegMem,
dst: Writable<Reg>,
imm: u8,
size: OperandSize,
},
CallKnown {
dest: ExternalName,
opcode: Opcode,
info: Option<Box<CallInfo>>,
},
CallUnknown {
dest: RegMem,
opcode: Opcode,
info: Option<Box<CallInfo>>,
},
ReturnCallKnown {
callee: ExternalName,
info: Box<ReturnCallInfo>,
},
ReturnCallUnknown {
callee: RegMem,
info: Box<ReturnCallInfo>,
},
Args {
args: Vec<ArgPair>,
},
Rets {
rets: Vec<RetPair>,
},
Ret {
stack_bytes_to_pop: u32,
},
JmpKnown {
dst: MachLabel,
},
JmpIf {
cc: CC,
taken: MachLabel,
},
JmpCond {
cc: CC,
taken: MachLabel,
not_taken: MachLabel,
},
JmpTableSeq {
idx: Reg,
tmp1: Writable<Reg>,
tmp2: Writable<Reg>,
default_target: MachLabel,
targets: Box<Vec<MachLabel>>,
},
JmpUnknown {
target: RegMem,
},
TrapIf {
cc: CC,
trap_code: TrapCode,
},
TrapIfAnd {
cc1: CC,
cc2: CC,
trap_code: TrapCode,
},
TrapIfOr {
cc1: CC,
cc2: CC,
trap_code: TrapCode,
},
Hlt,
Ud2 {
trap_code: TrapCode,
},
LoadExtName {
dst: Writable<Reg>,
name: Box<ExternalName>,
offset: i64,
distance: RelocDistance,
},
LockCmpxchg {
ty: Type,
replacement: Reg,
expected: Reg,
mem: SyntheticAmode,
dst_old: Writable<Reg>,
},
AtomicRmwSeq {
ty: Type,
op: MachAtomicRmwOp,
mem: SyntheticAmode,
operand: Reg,
temp: Writable<Reg>,
dst_old: Writable<Reg>,
},
Fence {
kind: FenceKind,
},
VirtualSPOffsetAdj {
offset: i64,
},
XmmUninitializedValue {
dst: WritableXmm,
},
ElfTlsGetAddr {
symbol: ExternalName,
dst: WritableGpr,
},
MachOTlsGetAddr {
symbol: ExternalName,
dst: WritableGpr,
},
CoffTlsGetAddr {
symbol: ExternalName,
dst: WritableGpr,
tmp: WritableGpr,
},
Unwind {
inst: UnwindInst,
},
DummyUse {
reg: Reg,
},
}Expand description
Internal type MInst: defined at src/isa/x64/inst.isle line 8.
Variants§
Nop
AluRmiR
AluRM
AluRmRVex
AluConstOp
UnaryRmR
UnaryRmRVex
UnaryRmRImmVex
Not
Neg
Div
Div8
Mul
Mul8
IMul
IMulImm
CheckedSRemSeq
CheckedSRemSeq8
SignExtendData
Imm
MovRR
MovFromPReg
MovToPReg
MovzxRmR
Mov64MR
LoadEffectiveAddress
MovsxRmR
MovImmM
MovRM
ShiftR
XmmRmiReg
CmpRmiR
Setcc
Bswap
Cmove
XmmCmove
Push64
Pop64
Fields
§
dst: WritableGprStackProbeLoop
XmmRmR
XmmRmRUnaligned
XmmRmRBlend
XmmRmiRVex
XmmRmRImmVex
XmmVexPinsr
XmmRmRVex3
XmmRmRBlendVex
XmmUnaryRmRVex
XmmUnaryRmRImmVex
XmmMovRMVex
XmmMovRMImmVex
XmmToGprImmVex
GprToXmmVex
XmmToGprVex
XmmRmREvex
XmmUnaryRmRImmEvex
XmmRmREvex3
XmmUnaryRmR
XmmUnaryRmRUnaligned
XmmUnaryRmRImm
XmmUnaryRmREvex
XmmMovRM
XmmMovRMImm
XmmToGpr
XmmToGprImm
GprToXmm
CvtIntToFloat
CvtIntToFloatVex
CvtUint64ToFloatSeq
CvtFloatToSintSeq
Fields
§
dst_size: OperandSize§
src_size: OperandSize§
dst: WritableGpr§
tmp_gpr: WritableGpr§
tmp_xmm: WritableXmmCvtFloatToUintSeq
Fields
§
dst_size: OperandSize§
src_size: OperandSize§
dst: WritableGpr§
tmp_gpr: WritableGpr§
tmp_xmm: WritableXmm§
tmp_xmm2: WritableXmmXmmMinMaxSeq
XmmCmpRmR
XmmRmRImm
CallKnown
CallUnknown
ReturnCallKnown
ReturnCallUnknown
Args
Rets
Ret
JmpKnown
JmpIf
JmpCond
JmpTableSeq
Fields
JmpUnknown
TrapIf
TrapIfAnd
TrapIfOr
Hlt
Ud2
LoadExtName
LockCmpxchg
AtomicRmwSeq
Fence
VirtualSPOffsetAdj
XmmUninitializedValue
Fields
§
dst: WritableXmmElfTlsGetAddr
MachOTlsGetAddr
CoffTlsGetAddr
Unwind
Fields
§
inst: UnwindInstDummyUse
Trait Implementations§
source§impl MachInst for Inst
impl MachInst for Inst
§type ABIMachineSpec = X64ABIMachineSpec
type ABIMachineSpec = X64ABIMachineSpec
The ABI machine spec for this
MachInst.source§fn get_operands<F: Fn(VReg) -> VReg>(
&self,
collector: &mut OperandCollector<'_, F>
)
fn get_operands<F: Fn(VReg) -> VReg>( &self, collector: &mut OperandCollector<'_, F> )
Return the registers referenced by this machine instruction along with
the modes of reference (use, def, modify).
source§fn is_move(&self) -> Option<(Writable<Reg>, Reg)>
fn is_move(&self) -> Option<(Writable<Reg>, Reg)>
If this is a simple move, return the (source, destination) tuple of registers.
source§fn is_included_in_clobbers(&self) -> bool
fn is_included_in_clobbers(&self) -> bool
Should this instruction be included in the clobber-set?
source§fn is_term(&self) -> MachTerminator
fn is_term(&self) -> MachTerminator
Is this a terminator (branch or ret)? If so, return its type
(ret/uncond/cond) and target if applicable.
source§fn is_mem_access(&self) -> bool
fn is_mem_access(&self) -> bool
Does this instruction access memory?
source§fn gen_nop(preferred_size: usize) -> Inst
fn gen_nop(preferred_size: usize) -> Inst
Generate a NOP. The
preferred_size parameter allows the caller to
request a NOP of that size, or as close to it as possible. The machine
backend may return a NOP whose binary encoding is smaller than the
preferred size, but must not return a NOP that is larger. However,
the instruction must have a nonzero size if preferred_size is nonzero.source§fn rc_for_type(
ty: Type
) -> CodegenResult<(&'static [RegClass], &'static [Type])>
fn rc_for_type( ty: Type ) -> CodegenResult<(&'static [RegClass], &'static [Type])>
Determine register class(es) to store the given Cranelift type, and the
Cranelift type actually stored in the underlying register(s). May return
an error if the type isn’t supported by this backend. Read more
source§fn canonical_type_for_rc(rc: RegClass) -> Type
fn canonical_type_for_rc(rc: RegClass) -> Type
Get an appropriate type that can fully hold a value in a given
register class. This may not be the only type that maps to
that class, but when used with
gen_move() or the ABI trait’s
load/spill constructors, it should produce instruction(s) that
move the entire register contents.source§fn gen_jump(label: MachLabel) -> Inst
fn gen_jump(label: MachLabel) -> Inst
Generate a jump to another target. Used during lowering of
control flow.
source§fn gen_imm_u64(value: u64, dst: Writable<Reg>) -> Option<Self>
fn gen_imm_u64(value: u64, dst: Writable<Reg>) -> Option<Self>
Generate a store of an immediate 64-bit integer to a register. Used by
the control plane to generate random instructions.
source§fn gen_imm_f64(
value: f64,
tmp: Writable<Reg>,
dst: Writable<Reg>
) -> SmallVec<[Self; 2]>
fn gen_imm_f64( value: f64, tmp: Writable<Reg>, dst: Writable<Reg> ) -> SmallVec<[Self; 2]>
Generate a store of an immediate 64-bit integer to a register. Used by
the control plane to generate random instructions. The tmp register may
be used by architectures which don’t support writing immediate values to
floating point registers directly.
source§fn gen_dummy_use(reg: Reg) -> Self
fn gen_dummy_use(reg: Reg) -> Self
Generate a dummy instruction that will keep a value alive but
has no other purpose.
source§fn worst_case_size() -> CodeOffset
fn worst_case_size() -> CodeOffset
What is the worst-case instruction size emitted by this instruction type?
source§fn ref_type_regclass(_: &Flags) -> RegClass
fn ref_type_regclass(_: &Flags) -> RegClass
What is the register class used for reference types (GC-observable pointers)? Can
be dependent on compilation flags.
source§fn is_safepoint(&self) -> bool
fn is_safepoint(&self) -> bool
Is this a safepoint?
source§fn function_alignment() -> FunctionAlignment
fn function_alignment() -> FunctionAlignment
Returns a description of the alignment required for functions for this
architecture.
§type LabelUse = LabelUse
type LabelUse = LabelUse
A label-use kind: a type that describes the types of label references that
can occur in an instruction.
source§const TRAP_OPCODE: &'static [u8] = _
const TRAP_OPCODE: &'static [u8] = _
Byte representation of a trap opcode which is inserted by
MachBuffer
during its defer_trap method.source§fn align_basic_block(offset: CodeOffset) -> CodeOffset
fn align_basic_block(offset: CodeOffset) -> CodeOffset
Align a basic block offset (from start of function). By default, no
alignment occurs.
source§impl MachInstEmit for Inst
impl MachInstEmit for Inst
source§fn emit(
&self,
allocs: &[Allocation],
sink: &mut MachBuffer<Inst>,
info: &Self::Info,
state: &mut Self::State
)
fn emit( &self, allocs: &[Allocation], sink: &mut MachBuffer<Inst>, info: &Self::Info, state: &mut Self::State )
Emit the instruction.
source§fn pretty_print_inst(
&self,
allocs: &[Allocation],
_: &mut Self::State
) -> String
fn pretty_print_inst( &self, allocs: &[Allocation], _: &mut Self::State ) -> String
Pretty-print the instruction.
source§impl MachInstEmitState<MInst> for EmitState
impl MachInstEmitState<MInst> for EmitState
source§fn new(abi: &Callee<X64ABIMachineSpec>, ctrl_plane: ControlPlane) -> Self
fn new(abi: &Callee<X64ABIMachineSpec>, ctrl_plane: ControlPlane) -> Self
Create a new emission state given the ABI object.
source§fn pre_safepoint(&mut self, stack_map: StackMap)
fn pre_safepoint(&mut self, stack_map: StackMap)
Update the emission state before emitting an instruction that is a
safepoint.
source§fn pre_sourceloc(&mut self, srcloc: RelSourceLoc)
fn pre_sourceloc(&mut self, srcloc: RelSourceLoc)
Update the emission state to indicate instructions are associated with a
particular RelSourceLoc.
source§fn ctrl_plane_mut(&mut self) -> &mut ControlPlane
fn ctrl_plane_mut(&mut self) -> &mut ControlPlane
The emission state holds ownership of a control plane, so it doesn’t
have to be passed around explicitly too much.
ctrl_plane_mut may
be used if temporary access to the control plane is needed by some
other function that doesn’t have access to the emission state.source§fn take_ctrl_plane(self) -> ControlPlane
fn take_ctrl_plane(self) -> ControlPlane
Used to continue using a control plane after the emission state is
not needed anymore.
source§fn on_new_block(&mut self)
fn on_new_block(&mut self)
A hook that triggers when first emitting a new block.
It is guaranteed to be called before any instructions are emitted.
Auto Trait Implementations§
impl Freeze for MInst
impl RefUnwindSafe for MInst
impl Send for MInst
impl Sync for MInst
impl Unpin for MInst
impl UnwindSafe for MInst
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more